Layout Engineer, DPG IP DEV Layout

... Address: C/O TCS - Deccan Park - Hyd Deccan Park Plot No 1 Software Units Layout MadhapurHyderabadTSINDIA500081 Facility: TCS - DECCAN PARK Qualification: Diploma Experience: 202 - 202 years Source: Sodexo India | Job Code: IJP573570

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. ASIC IP STA Engineer (6-10 Years) | DDR PHY / ONFI PHY / IO Expander Location: Bengaluru, India Experience: 6-10 Years Enducational Qualification : BE/B-Tech/M-Tech (EEE, ECE, Micron Electronics, VLSI) Key Requirements Member of the AMS IP Physical Design team , responsible for post-layout STA signoff and timing closure of high-speed interface IPs, with close collaboration across IP Design, SoC Synthesis, and SoC Physical Design teams throughout IP development and SoC integration. 6-10 years of experience in Static Timing Analysis (STA) with a proven track record of 4 &#43; successful tapeouts . Strong hands-on expertise with Cadence Tempus (preferred). In-depth experience in MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes. Experience working on high-speed Memory Interface IPs such as DDR PHY, ONFI PHY, IO Expander (IOE) , or similar high-performance interface designs. Strong understanding of timing constraints development, validation, and debug , including clocks, generated clocks, timing exceptions, and mode-specific constraints. Experience in Liberty (.lib) and ETM timing model generation, validation, correlation, and quality assessment . <span

Role: Network Engineer Location: Gurgaon Graviton is a privately funded quantitative trading firm striving for excellence in financial markets' research. We are seeking a Network Engineer for our team in Gurgaon. Graviton trades across a multitude of asset classes and trading venues using a gamut of concepts and techniques ranging from time series analysis, filtering, classification, stochastic models, pattern recognition to statistical inference analysing terabytes of data to come up with ideas to identify pricing anomalies in financial markets. Key Responsibilities Design, deploy, operate, and troubleshoot low-latency network infrastructure used by trading firms. Manage connectivity to global stock exchanges, brokers, market-data providers, and ISPs. Build and maintain colocation infrastructure including routers, switches, Layer-1 devices (added advantage), structured cabling and cross connects. Configure and support Cisco Nexus, Arista and similar platform devices. Design and troubleshoot Layer 2 and Layer 3 networks including: VLANs, VRFs, BGP, OSPF, Static routing, PIM, IGMP, Multicast, SSM, ACLs and QoS. Troubleshoot packet loss, multicast issues, duplicate packets, IGMP/PIM and multicast/BGP routing. Monitor and optimize latency, jitter, packet loss, interface errors, congestion, and network performance. Work with ultra-low-latency technologies including: Cut-through switching, Layer-1 switches, FPGA-based network devices, Kernel-bypass networking, ExaNIC/Solarflare NICs, Hardware timestamping. Configure and troubleshoot PTP and clock synchronization infrastructure. Perform server and network equipment installation in exchange and third-party data centres. Manage rack layout, patching, cable optimization, optics, DACs, cross-connects, and inventory. Coordinate network changes with exchanges, telecom providers, brokers, vendors, and data-centre teams. Plan and execute production changes during approved maintenance windows. Perform pre-change validation, c

Silicon Physical Design Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, fo

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs

About DevRev At DevRev, we're building the future of work with Computer – your AI teammate. Unlike traditional tools, Computer unifies all your data sources, tools, and workflows into a single AI-ready platform, giving employees real-time insights, proactive suggestions, and powerful agentic actions. It extends your existing software with AI-native apps and agents that work alongside your teams and customers – updating workflows, coordinating across teams, and eliminating repetitive work. We call this Team Intelligence: human-AI collaboration that breaks down silos, brings people back together, and frees you to solve bigger problems. Backed by Khosla Ventures and Mayfield with $150M+ raised, DevRev is trusted by global companies across industries. About the role You'll define the design infrastructure that every product team at DevRev builds on. Where L4 designers own specific product areas, your work is more structural: evolving Arcade (our design system), defining global interaction patterns, building design tooling, and ensuring that foundational decisions compound across the platform rather than fragment. You're part designer, part design engineer - someone who thinks architecturally and isn't afraid to get into code, prototyping environments, or toolchain automation to make the whole team faster and more consistent. What you'll do Shape Arcade's architectural evolution - identifying when the system can't support new needs and proposing solutions that maintain coherence. Define global patterns that multiple product teams adopt: layout systems, responsive behaviour, data display conventions, navigation structures. Build and maintain design tooling - Figma plugins, prototyping infrastructure, token pipelines, documentation systems - that accelerate the work of others. Prototype at the systems level to de-risk architectural decisions before they're expensive to reverse. Pioneer interaction patterns for Computer's conversational paradigm - designing for the e