Cpu Core Design Verification Test Generator Lead Jobs

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers. You will own CPU focused test generator development and verification strategy, shaping how our out-of-order RISC-V CPUs are validated against complex ISA and microarchitectural behavior. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU design verification, test generation, or closely related CPU validation work. You have led development of test generators for x86, ARM, or RISC-V ISA environments. You understand CPU ISA behavior, privileged architecture, and high-performance out-of-order CPU microarchitecture. You are comfortable building tools, stimulus, and automation that scale verification across large CPU programs. You communicate clearly across design, DV, architecture, emulation, and post-silicon teams. What We Need Lead development of CPU core-level test generators for high-performance out-of-order RISC-V cores. Own generator strategy, infrastructure, and methodology for ISA and microarchitectural verification in both pre-silico

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking a Verification Lead for our next-generation AI hardware. You’ll guide a top-tier team of Verification Engineers, shaping test strategies to validate functionality and performance of our AI core. This role requires expertise in AI-specific data types, common AI data-movement compute patterns, and on-chip network validation, combined with strong leadership and collaboration skills. This role is hybrid, based out Toronto, ON. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A Seasoned Verification Leader: An experienced ASIC/SoC lead with proven track record of leading teams through complex tape-outs. An AI Hardware Specialist: An expert in the nuances of high-performance compute, specifically focused on AI/ML architectures and the intricacies of tensor-based operations. A Systems Architect at Heart: A strategist who views verification through a system-level lens, ensuring that hardware, software, and on-chip networks (NoC) harmonize perfectly. A Technical Mentor: A hands-on guide proficient in UVM, SystemVerilog, and cocotb, dedicated to elevating team capabilities and driving rigorous coverage-driven methodologies. What We

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers. You will own CPU core-level testbench development and verification, shaping how our out-of-order RISC-V CPUs behave in silicon. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU verification, CPU testbench development, or closely related digital design. You have deep hands-on experience building and owning CPU core-level testbenches, not just using existing environments. You know high-performance out-of-order CPU microarchitecture in depth. You are comfortable developing testbench infrastructure in CVM methodology, with UVM experience as a strong plus. You work comfortably across RTL, waveforms, logs, regressions, and cross-functional debug with design, DV, emulation, and post-silicon teams. You are comfortable using AI-assisted verification workflows to improve debug, stimulus creation, and coverage analysis, while applying strong engineering judgment to validate results. What We Need Lead hands-on CPU core-level testbench development for hi

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers. You will lead our Bangalore-based CPU Core Design Verification team, driving both the technical strategy and the people leadership behind verification of our high-performance, out-of-order RISC-V CPUs. You will manage a team of core-level verification engineers, partner closely with our Santa Clara and Austin sites, and own delivery of core verification from architecture definition through tapeout readiness. This role is hybrid based out of Bangalore, India, with regular collaboration across our globally distributed CPU organization. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are 15+ years of CPU/DV experience, including 7+ years leading verification teams, with strong hands-on expertise in high-performance, out-of-order CPU verification. Deep microarchitecture & verification expertise, including ISA, RTL, UVM/CVM, testbench development, regressions, coverage, and complex debug. Strong people and technical leadership, with experience hiring, mentoring, developing engineers, and setting verification strategy and methodology across teams. Highly

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers.You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU verification or closely related digital design. You know high‑performance out‑of‑order CPU microarchitecture in depth. You work comfortably with RTL, waveforms, logs, and complex debug scenarios. You communicate clearly across design, DV, emulation, and post‑silicon teams. What We Need Plan and drive functional verification for CPU core features and complex microarchitectural scenarios. Develop UVM, assembly, and C/C++ based stimulus, functional models, and coverage for ISA, RISC-V extensions, and un-core components. Debug simulation and emulation regressions using RTL understanding, waveforms, and logs to identify and resolve issues efficiently. Build and enhance coverage models, testbenches, and debug infrastructure to improve verification quality and coverage closure. Collaborate with design, validation, and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to drive infrastructure for performance analysis, correlation and verification. You’ll work on a CPU based on RISC-V ISA, collaborating with core architects and RTL teams to deliver a highly efficient and performant design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Strong problem solver who can identify complex issues, develop practical solutions, and drive them through implementation. Enjoy building tools and improving the infrastructure, workflows, and methodologies that make CPU development more efficient. Skilled in C++ and Python, with experience using industry-standard compilation, simulation, and emulation tools. Experience with verification infrastructure and methodologies along with knowledge of high-performance CPU architecture and microarchitecture. Proficient in debugging RTL and logic across multiple design hierarchies and pre-silicon environments. What We Need Join a team driving improvements in CPU microarchitecture, verifying performance, and correlating results between RTL and the performance mode

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team and lead the front-end RTL physical implementation team. Drive CAD flows on multiple process technologies while working closely with core micro-architects to refine CPU core configurations and optimizing PPA. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, RTL and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An expert in physical design practices used to optimize PPA Experienced in high-performance physical design. Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis. Skilled in synthesis, place and route tools including flows and physical design methodology. Background in CPU micro-architecture. What We Need Own front‑end physical implementation and PPA definition for a high‑performance RISC‑V CPU and CPU subsystem Work closely with microarchitects and RTL designers to “make the IP better” by optimizing frequency, power, and area

NK Securities Research is a leading financial firm that leverages cutting-edge technology and sophisticated algorithms to trade the financial markets. Founded in 2011, we have gained invaluable experience in the field of High-Frequency Trading (HFT) across different asset classes. Role Overview We’re looking for engineers who can take AI work beyond experiments and make it hold up in production. You’ll work closely with quant researchers and infra engineers to build AI systems that actually get used improving research speed and internal tooling without slowing down the core stack. We value engineers who think about trade-offs, test what they build, and care about how things run in production. What You’ll Build Production AI Ship models that meet defined latency and reliability expectation Add monitoring, rollback, and guardrails before anything goes live Optimise inference across CPU/GPU environments when it matters Integration into Real Systems Plug AI into data-heavy workflows without hurting performance Work within existing low-latency architecture instead of fighting it Profile and remove bottlenecks rather than guessing AI for Engineers & Researchers Build tools that genuinely speed up research and development Improve code understanding, review workflows, and internal knowledge retrieval Keep systems auditable and predictable LLM & Retrieval Systems Implement structured RAG and embedding pipelines with validation in place Create safe integration layers between models and internal systems Performance & Standards Track latency, drift, and stability — not just accuracy Build observability into everything you ship Help raise the bar for how AI is engineered here What We’re Looking For Strong Python fundamentals Clear thinking around system design and performance trade-offs Experience deploying AI systems in production (1–5 years is typical) Familiarity with transformers, embeddings, or LLM deployment Nice to have: Exposure to C++ / Rust / Go E

Job Overview: We are seeking a high-caliber Rust Systems Engineer to design, build, and optimize high-throughput, low-latency backend systems and infrastructure. In this role, you will go beyond web APIs—tackling low-level performance bottlenecks, complex state management, parallel compute algorithms, and concurrent data processing pipelines. If you thrive on deterministic memory management, zero-cost abstractions, and writing safe, blazingly fast concurrent systems, this role is for you. Key Responsibilities: High-Performance Architecture: Design and implement zero-cost, high-throughput, low-latency engine components and data processing pipelines in Rust. Concurrent & Thread-Safe Systems: Build thread-safe, lock-free, or fine-grained locked data structures and state machines capable of scaling across multi-core architectures without race conditions. Priority & Real-Time Threading: Design custom thread pools, task schedulers, and execution queues with priority-based task scheduling and resource allocation controls. Algorithmic Optimization: Implement complex computational logic, including high-efficiency recursive algorithms, tail-call optimizations, and dynamic cache-friendly data structures. Resource & Memory Management: Leverage Rust’s ownership model, lifetime annotations, custom allocators, and non-blocking I/O to achieve predictable low-latency profiling (minimizing allocations and cash misses). System Profiling & Benchmarking: Conduct continuous benchmarking (criterion), flame graph analysis, memory profiling (Val grind/heap track), and CPU SIMD/vectorization optimizations. Key Skills: Core Rust & Functional Programming: Advanced Rust Mastery: Deep experience with Rust internals (stdsync, stdcell, custom Drop, unsafe Rust boundaries, and macro systems). Closures & Higher-Order Functions: Mastery of Rust’s functional traits (Fn, FnMut, FnOnce), capturing environments, move semantics within closures, and passing unboxed closures for zero

Location: San Francisco, CA (Hybrid: 4 days onsite/week). Relocation assistance available. About the Team: We build foundational platform software that enables reliable, secure, and performant products. The team works across system layers and partners closely with adjacent engineering groups to deliver robust capabilities from concept through launch. About the Role: We’re seeking a System Software Engineer to design, implement, and debug core platform components and the pipelines that build and update system images. You’ll work across operating system layers, focusing on performance, security, and deep system debugging to ship production‑grade systems. In this role, you will: Design, implement, and debug system‑level components and services across kernel and user space. Configure and maintain OS platform services (init, services, networking, security policies) and related tooling. Build and operate image and update pipelines, ensuring reliability, reproducibility, and rollback safety. Instrument and analyze performance using profiling and tracing; optimize CPU, memory, I/O, and power usage. Own platform observability and reliability: logging, crash capture, watchdogs, and diagnostics. Collaborate with cross‑functional teams to define interfaces and deliver end‑to‑end features. Establish strong engineering practices: code review, CI, reproducible builds, and release management. Partner with external suppliers to support builds and deployments. You might thrive in this role if you: Have shipped production systems software on modern operating systems. Are proficient in C/C++ and a scripting language, and comfortable with OS internals (concurrency, memory management, filesystems, networking, power management). Bring strong systems debugging skills using debuggers, tracers, profilers, and logs across kernel/user‑space boundaries. Understand configuration of platform services and interfaces, and can translate requirements into stable, well‑documented APIs. Are fluent in u

Here at Appian, our values of Intensity and Excellence define who we are. We set high standards and live up to them, ensuring that everything we do is done with care and quality. We approach every challenge with ambition and commitment, holding ourselves and each other accountable to achieve the best results. When you join Appian, you’ll be part of a passionate team dedicated to accomplishing hard things, together. Senior Consultant Location: Chennai, India | Work Model: In Office Appian Customer Success is obsessed with delivering exceptional customer outcomes and driving mission-critical business impact. Grounded in our core values of Excellence and Intensity, we act as elite technical advisors to our commercial clients. By joining this high-performance team, you will champion a culture of candid communication and excellence while accelerating global adoption of our AI-Powered Process Automation platform. What You’ll Do Implement Scalable Platform Architecture: Build and maintain standards and tools to ensure high performance and resilience with a focus on reusability, schema design, data modeling , query performance, and responsive UX/UI best practices. Engineered Integrations: Perform hands-on design, code implementation, and unit testing using SQL views , stored procedures , and high-concurrency REST/SOAP web services/APIs . System-Level Troubleshooting: Rapidly diagnose performance bottlenecks, memory usage, CPU constraints, and network latency spikes across the web application stack. Performance Profiling & Analysis: Analyze database execution plans, system logs, and Locust load test outputs to isolate and resolve root-cause performance bottlenecks. Technical Quality & Enablement: Ensure continuous integration and delivery alignment by applying strong DevSecOps practices, robust automated testing, and clean coding standards. Required Qualifications Bachelor’s Degree in Computer Science, Engineering, Information Systems, or Mathematics. 8+ years of pro

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a skilled Software Engineer with a passion for building high-performance, low-level systems software. In this role, you’ll contribute to the development and optimization of the infrastructure that powers our cutting-edge processors, with a primary focus on C/C++ development and low-level programming. You'll work closely with large inference and training model development to further drive Scale Out software and hardware performance. This role is hybrid, based out of Toronto, ON. Who You Are Strong C or C++ systems engineer with a deep understanding of memory, threading, I/O, and low-level execution models. Experienced building low-level software, drivers, embedded systems, or performance-critical infrastructure. Comfortable working close to hardware and curious about how systems behave under the hood. Proficient with Linux systems programming and debugging tools such as gdb, strace, and perf. Structured problem solver who thrives in fast-paced, highly technical environments. What We Need Design, develop, and maintain core infrastructure software that interfaces directly with Tenstorrent hardware. Build low-level libraries and APIs for communication and synchronization across compute nodes. Optimize system-level software for performance, scalability, and reliability in distributed environments. Support hardware

About the Team The Workload Networking team is responsible for the collective communication stack used in our largest training jobs. Using a combination of C++ and CUDA we work on novel collective communication techniques that enable efficient training of our flagship models on our largest custom built supercomputers. The models we train are key ingredients to the AI research progress at OpenAI and the field as a whole, and we continually incorporate learnings from our entire research org into our training platform. About the Role As a Software Engineer, Networking you will design and implement custom networking collectives that are tightly integrated into our training stack. We’re looking for people who have a background in low level performance critical software. Experience with collective communication is a bonus. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Collaborate closely with ML researchers to design and implement efficient collective operations in C++ and CUDA. Ensure that our largest training jobs take full advantage of the different network transports used in our supercomputers. Work on simulations to inform our future supercomputer network designs. You might thrive in this role if you: Have written distributed algorithms using RDMA in the past. Are comfortable writing low level performance sensitive CPU and/or GPU code. Are familiar with network simulation techniques. About OpenAI OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voic

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Curious about how cutting-edge hardware actually comes to life? We're looking for someone who’s excited to dive into the core of next-gen systems and help make them real. In this role, you’ll validate high-speed interfaces, solve complex system-level puzzles, and collaborate across teams to shape the future of AI/ML computing. If firmware, hardware, and hands-on debugging sound like your kind of fun — let’s chat! This role is hybrid and based in Vancouver, Canada. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You love bringing hardware to life and enjoy the thrill of solving tricky problems across the hardware–firmware boundary. You’re hands-on in the lab and comfortable with tools like oscilloscopes, protocol analyzers, and JTAG — digging deep doesn’t scare you. You’re comfortable jumping into unfamiliar problems and figuring things out — whether it’s in the lab or in firmware. You’re curious, collaborative, and excited to work on technology that pushes the boundaries of performance. What We Need Someone to take the lead in validating our next-gen PCIe interfaces — from controller to PHY, and everything in between. A strong co

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a Director of Accounting Operations to lead and scale the company’s core accounting operations function. This leader will build a disciplined, accurate, audit-ready, and scalable organization that can support rapid growth, global expansion, increasing transaction complexity, and future public-company requirements. In this role, you will oversee day-to-day accounting operations across AP, AR, payroll accounting, fixed assets, accruals, reconciliations, and close operations while partnering across global finance functions. This role is hybrid, based out of Santa Clara,CA; Austin,TX; Boston, MA; or Toronto, ON. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An experienced accounting operations leader who thrives in fast-paced, high-growth environments and brings strong technical accounting judgment, operational discipline, and a builder’s mindset. Equally comfortable solving detailed accounting issues and designing scalable processes, systems, and controls, with a strong foundation in US GAAP, close, reconciliations, accruals, AP, AR, payroll accounting, fixed assets, internal controls, and audit support. Able to tell wha