Design Engineer in Bengaluru

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs

About Us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Job Summary Working within the logical design team, the silicon logical design engineer is responsible for a wide range of logical design tasks. The team is responsible for delivering the Microarchitecture and RTL design to implement the chip architecture specification for Graphcore Silicon, working closely with other engineers within the Silicon team. The successful candidate will be responsible for helping the team deliver high quality micro-architecture and RTL for Graphcore chips, working within the logical design team and with the broader Silicon team to ensure we meet the company objectives for Silicon delivery. Responsibilities and Duties Integrate IP and subsystems into top-level SoC designs Develop and maintain build and configuration environments Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level Support verification and physical design teams through clean interface hand-offs Debug and resolve integration-related issues across multiple hierarchies Contribute to the continuous improvement of integration flows and automation Producing high quality microarchitecture and other documentation Ensure good communication between sites to maintain consistent working practises Candidate Profile Essential skills: Logical design experience in relevant industry Experience range 8-12 years in Semiconductor Industry/Product development exposure. Be highly motivated, a self-starter, and a team player Ability to work across teams and debugging issues seen to find root cau

Silicon Physical Design Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, fo

About Us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Job Summary Working within the logical design team, the silicon logical design engineer is responsible for a wide range of logical design tasks. The team is responsible for delivering the Microarchitecture and RTL design to implement the chip architecture specification for Graphcore Silicon, working closely with other engineers within the Silicon team. The successful candidate will be responsible for helping the team deliver high quality micro-architecture and RTL for Graphcore chips, working within the logical design team and with the broader Silicon team to ensure we meet the company objectives for Silicon delivery. Responsibilities and Duties Integrate IP and subsystems into top-level SoC designs Develop and maintain build and configuration environments Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level Support verification and physical design teams through clean interface hand-offs Debug and resolve integration-related issues across multiple hierarchies Contribute to the continuous improvement of integration flows and automation Producing high quality microarchitecture and other documentation Ensure good communication between sites to maintain consistent working practises Candidate Profile Essential skills: Logical design experience in relevant industry Experience range 4-8 years in Semiconductor Industry/Product development exposure. Be highly motivated, a self-starter, and a team player Ability to work across teams and debugging issues seen to find root caus

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a hands-on RTL Design Engineer to own the microarchitecture and RTL implementation of the Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller . You’ll collaborate with cross-functional teams—architecture, firmware, software, DV, and PD—to define, design, and optimize power management solutions for next-generation RISC-V/ARM-based SoCs. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels. During the interview process, you will beevaluated and offered a level that aligns with your experience, which may differ from the one in this posting. Who You Are 5–10 years of experience in ASIC/SOC/IP design, with hands-on experience in microarchitecture and RTL development Skilled in Verilog/SystemVerilog and comfortable working across design, debug, and analysis Design and develop microarchitectures for a set of highly configurable IPs Microarchitecture and RTL coding ensuring optimal performance, power, area Work with verification teams on assertions, test plans, debug, coverage, etc. Deep understanding of power management concepts—clocking, reset, DVFS, and low-power modes Familiar with RISC-V or ARM-based SoCs and standard bus protocols (AXI, AHB, APB, CHI) Awareness of functional safety (ISO 26262) practices in hardware design What We Need Abil

About DevRev At DevRev, we're building the future of work with Computer – your AI teammate. Unlike traditional tools, Computer unifies all your data sources, tools, and workflows into a single AI-ready platform, giving employees real-time insights, proactive suggestions, and powerful agentic actions. It extends your existing software with AI-native apps and agents that work alongside your teams and customers – updating workflows, coordinating across teams, and eliminating repetitive work. We call this Team Intelligence: human-AI collaboration that breaks down silos, brings people back together, and frees you to solve bigger problems. Backed by Khosla Ventures and Mayfield with $150M+ raised, DevRev is trusted by global companies across industries. About the role You'll define the design infrastructure that every product team at DevRev builds on. Where L4 designers own specific product areas, your work is more structural: evolving Arcade (our design system), defining global interaction patterns, building design tooling, and ensuring that foundational decisions compound across the platform rather than fragment. You're part designer, part design engineer - someone who thinks architecturally and isn't afraid to get into code, prototyping environments, or toolchain automation to make the whole team faster and more consistent. What you'll do Shape Arcade's architectural evolution - identifying when the system can't support new needs and proposing solutions that maintain coherence. Define global patterns that multiple product teams adopt: layout systems, responsive behaviour, data display conventions, navigation structures. Build and maintain design tooling - Figma plugins, prototyping infrastructure, token pipelines, documentation systems - that accelerate the work of others. Prototype at the systems level to de-risk architectural decisions before they're expensive to reverse. Pioneer interaction patterns for Computer's conversational paradigm - designing for the e

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a highly skilled and motivated Senior Design Verification Engineer to join our team. In this role, you will be responsible for the end-to-end verification of our IOMMU (Input/Output Memory Management Unit) IP. You will play a critical role in ensuring the functional correctness and performance of the design, taking ownership of the verification process right from the initial specification understanding down to final coverage closure. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have hands-on experience in ASIC or SoC verification using SystemVerilog and UVM. You enjoy debugging complex design and verification issues and working closely with cross-functional teams. You’re comfortable building verification environments from scratch and driving coverage closure. You have familiarity with standard bus protocols and modern verification tools. What We Need Experience owning block or subsystem-level verification from test planning to sign-off. Strong understanding of constrained-random verification, coverage analysis, and regression debugging. Familiarity with proto

SonicWall is a cybersecurity forerunner with more than 30 years of expertise and is recognized as a leading partner-first company, ensuring our partners and their customers are never alone in the fight against cybercrime. With the ability to build, scale and manage security across the cloud, hybrid and traditional environments in real-time, SonicWall provides relentless security against the most evasive cyberattacks across endless exposure points for increasingly remote, mobile and cloud-enabled users. With its own threat research center, SonicWall can quickly and economically provide purpose-built security solutions to enable any organization—enterprise, government agencies and SMBs—around the world. For more information, visit www.sonicwall.com or follow us on Twitter , LinkedIn , Facebook and Instagram . Position Summary We are hiring a Software Dev Engineer to design, build, test, and deploy AI-powered applications. You will work across the full application lifecycle — from architecture and implementation through automated testing, CI/CD deployment, and production monitoring — building features that put large language models and agentic tooling to work inside SonicWall's internal systems. This is a hands-on engineering role for someone with 6–8 years of professional software development experience who is comfortable owning services end to end: writing production-quality code, integrating LLM and agentic APIs, standing up reliable data and retrieval pipelines, and shipping through a disciplined test-and-release process. You will collaborate closely with senior engineers, product stakeholders, and platform teams to turn requirements into dependable, well-tested applications. Key Responsibilities Develop AI applications: Design and build features and services that use LLM and agentic capabilities — prompting, tool/function calling, retrieval-augmented generation (RAG

Senior Machine Learning Engineer Description - We are looking for a Senior MLOps Engineer to design, build, and operate the infrastructure that enables machine learning models and large language models to be deployed safely, reliably, and at scale. In this role, you will create the end-to-end capabilities required to move models from experimentation into production, expose them through secure and highly available endpoints, and enable users and applications to interact with AI-powered services. You will work across AWS and Databricks to establish robust CI/CD pipelines, model-serving infrastructure, observability, governance, rollback mechanisms, and operational standards. You will partner closely with data scientists, machine learning engineers, software engineers, security teams, and platform engineers. The ideal candidate combines strong cloud and DevOps engineering skills with a practical understanding of machine learning systems, LLM deployment patterns, and production reliability. Key Responsibilities MLOps Platform and Architecture Design and implement a scalable MLOps platform using AWS and Databricks. Define reference architectures and reusable deployment patterns for traditional machine learning models, deep learning models, and large language models. Build standardized workflows that move models from development and validation into staging and production. Develop self-service capabilities that allow data scientists and ML engineers to deploy models without manually managing infrastructure. Establish clear separation between development, testing, staging, and production environments. Design multi-region or multi-availability-zone architectures where required by business continuity and availability objectives. CI/CD and

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE Join the Pipeline Engineering team at Everpure™ as a Software Engineer to build, own, and operationally scale the microservices and Temporal workflows driving continuous integration for FlashArray, FlashBlade, and Hyperscale. In this developer-first role based in Bangalore, you will design durable production services and agentic AI tools that directly reduce time-to-signal, optimize compute utilization, and absorb operational toil across our global engineering workforce. WHAT YOU'LL DO Architect Deterministic CI Workflows: Design and deploy production microservices and durable Temporal workflows that make pipeline execution resilient, resumable, and fully debuggable for enterprise storage platforms. Optimize Compute & Testbed Utilization: Extend in-house scheduling logic and placement algorithms across bare-metal hardware and VM fleets to minimize queue times and maximize infrastructure efficiency. Build Operational AI Agents: Engineer RAG pipelines and agentic workflows over failure logs, vector stores, and test metadata to automate root-cause analysis, flake classification, and developer triage. Drive Platform Observability & Ownership: Establish key platform metrics—including time-to-signal and pass/flake rates—while operating your services end-to-end to ensure long-term stability and eliminate recurring failure modes. Collaborate Across Product Teams: Partner with platform and product engineering group

Roles and Responsibilities Develop and maintain web applications using ReactJS Write well-designed, efficient code Translate product requirements & user stories Work closely with UI/UX team to translate the design into actual implementation Participate in discussion, planning, and brainstorming with teammates and stakeholders to achieve project goals Maintain code and write unit tests to ensure the product is of the highest quality Qualifications & Experience Bachelor’s in computer science or relevant fields 1+ years of relevant experience in developing front-end for web based products. Experience in Javascript (ReactJS / Redux), HTML, CSS, SCSS, Webpack, TypeScript Building advanced responsive layouts. Strong sense of ownership Attitude for getting things done Experience using RESTful APIs Proficient with version control systems, especially GIT, a plus Will be involved in developing any enterprise systems like eCommerce, manufacturing, supply chain, etc.,

JOB TITLE Cloud Engineer A Career with point72’s technology team As Point72 reimagines the future of investing, our Technology team is constantly evolving our firm’s IT infrastructure and engineering capabilities, positioning us at the forefront of a rapidly evolving technology landscape. We’re a team of experts who experiment and work to discover new ways to harness open-source solutions, modern cloud architectures, and sophisticated Artificial Intelligence (AI) solutions, while embracing enterprise agile methodologies. Our commitment to building and innovating in the AI space provides the framework intended to drive smarter decision making and enhance how we build and operate our platforms and applications. As a member of Point72’s Technology team, we encourage and support your professional development from day one—helping you advance your technical skills, contribute innovative ideas, and satisfy your own intellectual curiosity—all while delivering real business impact for our multi-billion-dollar global business. What You'll Do Design, implement, and maintain scalable cloud infrastructure using Infrastructure as Code (IaC) with Terraform. Manage and optimize foundational platform for AWS/GCP/Azure services including IAM, Virtual Private Cloud networking, Cloud Security controls and policies, Cloud platform tools and automation to ensure scale, performance and security. Collaborate with development and operations teams to automate deployment and operational processes. Monitor cloud environments to maintain high availability and security standards. Participate in architectural discussions and contribute to the technical roadmap for cloud solutions. Implement best practices for cloud resource optimization and cost management. What's Required Bachelor’s degree in Computer Science, Engineering, or a related field. 5 to 10 years of experience in cloud infrastructure design and automation with optional experience in cloud networking. Proficiency in Infrastructur

JOB TITLE Software Engineer, Controller’s Technology A CAREER WITH POINT72’S TECHNOLOGY TEAM As Point72 reimagines the future of investing, our Technology group is constantly improving our company’s IT infrastructure, positioning us at the forefront of a rapidly evolving technology landscape. We’re a team of experts experimenting, discovering new ways to harness the power of open source solutions, and embracing enterprise agile methodology. We encourage professional development to ensure you bring innovative ideas to our products while satisfying your own intellectual curiosity. WHAT YOU’LL DO As a software engineer on the Controller’s Technology team, you will use your programming expertise to design, develop, and support ETL, data warehouse, process flow, PnL validation and adjustment tools, and PnL reporting framework to modernize the PnL reporting platform and streamline the business process. Build analytical tools on a next generation technology platform to facilitate understanding of performance for Firm management and portfolio managers as well the reporting requirements of our Finance, Operations, Audit, and Technology functions. Develop quantitative understanding of PnL process and data flow to anticipate new requirements Innovate and improve our capabilities to deliver high quality products to our business partners Solving complex and challenging problems through the application of creative and unique solutions using the latest technology WHAT’S REQUIRED Strong data engineering, analytics, ETL and reconciliation skills using T-SQL, Python, Airflow etc. Bachelor’s in computer science, or related technical field with 5 years of programming experience End-to-end system design, development, support, and user coordination experience Strong development skills using Python, or C#. Strong data visualization skills using JS/React etc. A plus to have prior experience in financial industry working with Risk, valuation

MeltPlan | Planning Engine for the Built Environment MeltPlan is building the “planning engine” for the $14 Tn construction industry, an AI system designed specifically to optimize decisions before construction begins. While design software optimizes use and aesthetics and construction software optimizes execution and control, MeltPlan is building the missing layer - software that optimizes decisions and tradeoffs upstream, before scope is locked, procurement begins, and change orders become inevitable. MeltPlan’s long-term goal is to help teams make construction “boring” by making planning more intense: surfacing constraints and tradeoffs early, aligning stakeholders before plans are frozen, and reducing the need for late-stage redlines, rework, and change orders. MeltPlan is founded by operators who have built at scale. Kanav previously co-founded Innovaccer, a $3Bn health-tech company focused on making US healthcare more affordable and accessible. He’s now applying that systems-level thinking to construction.He’s joined by Tanmaya Kala, former Project Executive at DPR Construction, who led large commercial, healthcare, and life sciences projects. We combine deep tech scale with real construction execution. What This Role Really Is We are hiring a UI Engineering Lead with minimum 10 years of work exp , to drive frontend architecture scalable UI systems, and user experience across internal and external applications. The role involves building modern web applications using React, TypeScript, Next.js, Vite, and TailwindCSS, while leading reusable component development and microfrontend architecture using Module Federation. You will work closely with product and engineering teams, integrate Firebase services, and ensure frontend quality through Playwright and Vitest testing frameworks. The ideal candidate should have strong expertise in frontend engineering, scalable design systems, and modern UI architecture. What You’ll Do Build and maintain scalable frontend

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. ASIC IP STA Engineer (6-10 Years) | DDR PHY / ONFI PHY / IO Expander Location: Bengaluru, India Experience: 6-10 Years Enducational Qualification : BE/B-Tech/M-Tech (EEE, ECE, Micron Electronics, VLSI) Key Requirements Member of the AMS IP Physical Design team , responsible for post-layout STA signoff and timing closure of high-speed interface IPs, with close collaboration across IP Design, SoC Synthesis, and SoC Physical Design teams throughout IP development and SoC integration. 6-10 years of experience in Static Timing Analysis (STA) with a proven track record of 4 &#43; successful tapeouts . Strong hands-on expertise with Cadence Tempus (preferred). In-depth experience in MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes. Experience working on high-speed Memory Interface IPs such as DDR PHY, ONFI PHY, IO Expander (IOE) , or similar high-performance interface designs. Strong understanding of timing constraints development, validation, and debug , including clocks, generated clocks, timing exceptions, and mode-specific constraints. Experience in Liberty (.lib) and ETM timing model generation, validation, correlation, and quality assessment . <span