Design Engineers Jobs

Design Engineers Autocad & Solidworks (DME/BE-Mech) Job Location : Coimbatore Thudiyalur / Kavundampalayam / Saravanampatti / Kovilpalayam / Karamadai / Pannimadai / Vellamadai / Periyanaickenpalayam Contact : 88702 66194 Qualification : DME / BE- Mech (with Autocad & Solidworks 3D Modeling) Freshers / Experience : 0 - 5 yrs Salary : Rs. 15000/- (for Freshers) Rs. 20000/- to 35000/- (based on experience and tool test) Timing : 9AM 6.30 PM (Day shift only) Sunday Holiday Contact : 88702 66194

NVIDIA Networking is a leading provider of innovative end-to-end InfiniBand and Ethernet connectivity solutions for servers and storage. Our portfolio includes adapter cards, switches, cables, and software designed to optimize Data Center performance with industry-leading bandwidth and scalability. We serve diverse sectors such as high-performance computing, enterprise, cloud computing, and Web 2.0. Our mission is to stay ahead of the market by delivering groundbreaking products and services. Our Ethernet solutions are tailored for industries like Media & Entertainment and any domain that benefits from advanced DataStream and TCP/IP acceleration. What You’ll Be Doing: Lead a team of 8+ mechanical design engineers. Define priorities, create project plans, and allocate resources for mechanical programs in coordination with Product Managers. Drive all electro-mechanical, automated JIG and thermal design aspects, of production test setups, ensure readiness of test and assembly infrastructure for high-volume manufacturing. Develop multiple early design concepts in fast-paced product development cycles. Lead task forces to investigate and resolve production issues, reliability concerns, and conduct failure analysis. Perform risk assessments and implement mitigation strategies during product design. What We Need to See: B.Sc. in Mechanical Engineering or higher. 10+ overall years of relevant experience including 4+ years of experience managing teams of engineers in R&D environment. Proven expertise in developing, testing, and manufacturing of complex automated connection systems with precise moving parts, pneumatic and electro-mechanical systems design. Strong hands-on experience with 3D CAD tools (Creo preferred) static and dynamic mechanical simulation Solid background in designing components and sub systems an

The way products get built is changing. Agents write a growing share of shipped interfaces, designers work in code, and a design system's output is bigger than a component library. At Datadog we're redefining ours for that world, and evolving how the product looks and feels at the same time. DRUIDS is the design system behind every Datadog surface, used daily by more than a hundred designers and thousands of engineers across thirty-plus products. You'll lead the team that owns it: designers and design engineers who set the system's direction, hold the quality bar for what ships, and build the tools that make designing in code the default way to work. The team partners closely with product designers, frontend engineers and PMs across the company. This is a hands-on leadership role in a technical, engineering-forward company. You'll be expected to have a point of view and defend it, to be the person the design org asks about quality, and to make the call when work isn't good enough yet. Much of what a design system should be right now hasn't been settled — here or anywhere else. If you're a designer who never stopped making things, and you'd rather decide what a system should be than maintain one that already exists, this is the role. At Datadog, we place value in our office culture - the relationships and collaboration it builds and the creativity it brings to the table. We operate as a hybrid workplace to ensure our Datadogs can create a work-life harmony that best fits them. What You'll Do Lead the team and set its direction Decide what DRUIDS owns, what it ships, and what stays with product teams. Own where the system goes next. Have a view on what a design system should be, and argue for it. Turn direction into a roadmap, and work with partners on what gets built and when. Coach the designers and design engineers on your team, be clear about what each person owns, and hire as the team grows. Own craft and quality Own the craft and quality of components, patterns,

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking talented Physical Design Engineers to implement high-performance partitions for an industry-leading AI SOC. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid, based out of Austin,TX or Santa Clara, CA or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are Experienced with synthesis and place-and-route flows, especially using Synopsys Design Compiler / Fusion Compiler and IC Compiler II. Comfortable in a small, cross-functional physical design team, owning a block or subsystem and partnering on tapeout milestones with clear communication and accountability. Ideally bring extra depth in areas such as UPF/multi-voltage power domains, SoC interface IP integration (e.g. I3C, UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementati

About Ramp Ramp is building the smart infrastructure for finance teams, embedded in the transaction flow of every dollar a business spends. We automate how over $200B in annualized spend flows in and out of 70,000+ companies: authorizing payments, flagging risk, categorizing spend, and closing books. The problems are high-stakes, data-dense, and unforgiving. We hire people with high agency and high urgency. We look for slope over intercept. We care less about where you trained and more about what you’ve built. At Ramp, everyone is a builder who owns problems end to end and makes consequential decisions that shape the outcome. The median Ramp customer saves 5% and grows revenue 16% in their first year – far in excess of businesses operating without Ramp. We believe every ambitious company deserves the same. If you want to build systems that directly shape how companies move and manage billions, Ramp is the place to do it. About the Role As a Design Engineer at Ramp, you sit at the intersection of design and front-end engineering. You bring ambitious ideas to life in real interfaces, prototype directly in code, validate with customers, and ship production experiences with a high bar for craft, performance, and reliability. Design at Ramp is AI first and builder led. Work starts in an LLM to clarify intent and constraints, moves into tools like Claude and Cursor to explore and build, is tested with real customers, and then comes into Figma for systems and polish. AI and self-serve research are default parts of the workflow, not side experiments. We are looking for multiple design engineers who think like a designer, code like a front-end engineer, and treat AI as a real collaborator. What You’ll Do Design and build high-craft product experiences: Own key surfaces end to end, from concept through production. Use layout, interaction, and motion to make complex behavior feel simple and safe. Work AI first with Cursor and Claude Code: Use LLMs, Cursor, and Claude Code as y

Who we are About Stripe Stripe is a financial infrastructure platform for businesses. Millions of companies—from the world's largest enterprises to the most ambitious startups—use Stripe to accept payments, grow their revenue, and accelerate new business opportunities. Our mission is to increase the GDP of the internet, and we have a staggering amount of work ahead. That means you have an unprecedented opportunity to put the global economy within everyone's reach while doing the most important work of your career. About the team Web Presence and Platform is organized into two pillars, each of which is grouped into pods that focus on the central tenets of Stripe's public mission. The Presence pillar creates industry-leading designs for Stripe's front door surfaces, educating customers about the power of our platform, sharing Stripe's ideas and expertise with the public, and driving adoption. The Platform pillar builds the internal machinery that powers these surfaces, and is responsible for making our websites fast, stable, and easy to update. Together we design and build stripe.com and other sites that amount to what is, for many, their first impression of Stripe. As such, WPP offers exciting opportunities to have a major impact on Stripe's success. We want to make every pixel count, we want it to be enthralling, and we want to help other Stripes seamlessly benefit from our systematic work. What you'll do As a Design Engineer you will concept, prototype, and build new experiences for our web presence. You'll bring your creativity and expertise to the full range of the Stripe brand, across evergreen pages as well as time-based campaigns. You'll both utilize and contribute to our libraries and design systems, and, when appropriate, work outside established systems to create new digital moments. You'll constantly have in-browser performance in mind, and create abstractions that other designers and engineers consume and build upon. All Design Engineers in WPP have a sha

Early Career Mechanical Design Engineer Company: The Boeing Company Boeing Test & Evaluation (BT&E) is looking for an Early Career Mechanical Design Engineer to support the Environmental Test Design Engineering team in Berkeley, MO. The primary focus of this position is to support St. Louis Environmental Lab testing for local Boeing Defense & Space (BDS) programs. The design team works in partnership with the lab test teams to provide the designs and hardware needed to complete testing. Test capabilities within the Environmental labs include vibrational/structural dynamics, acoustic, airflow systems, fuel flow systems, high temperature flow impingement, and environmental control chambers, where temperature, humidity, and pressure are varied. Mechanical Design Engineers on the team design and modify test articles, fixtures, and support structures that integrate with our lab facilities. Design work ranges from adapters and fixtures to full test rigs and complete aircraft subsystems with their support structures. Responsibilities include designing interfaces to facility infrastructure such as supplied pressure, heating/cooling, power, hydraulics, and a full suite of instrumentation. Design Engineers support fabrication, installation, connection, and acceptance/check-out to deliver test-ready hardware. Boeing St. Louis is building the future ‒ creating innovative solutions that will define the next generation of aerospace. As part of this team, you will have the opportunity to work on the latest military aircraft and weapons programs such as T-7A, F-15, F/A-18, MQ-25, JDAM, SDB, in addition to Phantom Works proprietary efforts. Position Responsibilities: Develop mechanical design criteria from

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer who will contribute to the physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout. You will partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs. Along the way, you will build end-to-end ASIC expertise while learning from experienced engineers across the chip development process. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An engineer excited to work on high-performance designs for industry-leading AI/ML architectures. A collaborative problem solver who enjoys working with experienced engineers across ASIC disciplines. Grounded in logic design fundamentals and gate- and transistor-level implementation. Curious about how early architectural and RTL decisions shape physical implementation and final chip quality. What We Need A BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a relat

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Design Technology Co-Optimization (DTCO) team works at the intersection of process technology, standard cell architecture, and design implementation to optimize power, performance, and area (PPA) for advanced memory products. The team collaborates closely with standard cell library, RTL, and physical design engineers to evaluate design tradeoffs and develop methodologies that improve silicon outcomes. As a DTCO Intern, you will gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level. You will use industry-standard place-and-route tools and AI-enabled automation techniques to implement, benchmark, and optimize logic blocks while developing practical skills in physical design, timing closure, and design analysis. Responsibilities Implement standard cell logic blocks using industry-standard physical design tools, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization activities focused on PPA assessment. Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations, identifying opportunities for improvement. Perform static timing analysis (STA), investigate setup and hold timing violations, and support timing closure activities. Execute physical verification checks, including DRC, LVS, and IR-drop analysis, and assist with resolving design issues. Leverage Generative AI, AI Assistants, and Agentic AI solutions to automate data collection, reporting, comparison, and w

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid , based out of Austin, TX, Santa Clara, CA or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts. Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration. Strong problem solver who excels at debugging complex issues across design hierarchies. Collaborative team player who thrives in fast-paced, technically challenging environments. What We Need BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs. Expertise with industry-

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs

Silicon Physical Design Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, fo

By submitting your resume, you’re expressing interest in our 2027 RDSS (Research and Development Substitute Services) program. Please confirm your eligibility with the local district office before applying the role. NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU & SOC acts as the brains of computers, robots, and self-driving cars that can understand the world. We are looking for Design Validation Engineer in Taipei for board/system power qualification and function test, responsible for NVIDIA Data Center platform, Graphics board, ARM Based platform and Autonomous Driving Platform. If you're creative and autonomous, we want to hear from you! What you'll be doing: Server/Motherboard/Mobile system functionality test. Clock/Sequency/GPIO signal measurement and verification. WAT (wide area test) function test. Gaming test. High/Low speed interface SI test. Co-work with hardware design engineers on debug and FA. Co-work with mechanical/thermal engineers for cooler/heatsink design. What we need to see: Masters degree in EE, computer science, or relative majors. Proficient with Linux system and GPU setup. Capable of writing simple shell scripts and analyzing test results using commands. Familiar with PC and Datacenter system hardware assembly, MB BIOS upgrade, and network troubleshooting Proficient with a programming language (C/C++, Python, Java, or Perl) Understand UEFI boot OS startup process and out-of-band (

About the Team OpenAI, in close collaboration with our capital partners, is embarking on a journey to build the world’s most advanced AI infrastructure ecosystem. This team is central to this mission, setting the core infra strategy and implementing this vision. From site selection to the buildout process, this team sits at the intersection of commercial, technical, strategy, and operations, interacting with teams and executives inside and outside of OpenAI. About the Role We are seeking experienced Data Center Mechanical and Electrical/Power Design Engineers with expertise in designing, operating, and maintaining large-scale data center campuses. The ideal candidate for this role will have extensive background and experience in design and managing critical equipment and facilities, design and operation of MEP (Mechanical, Electrical, Plumbing) systems, and overseeing operational activities from initial phases of Data Center build through delivery and ongoing maintenance. The ideal candidate will have a strong technical background, operational leadership experience, and a proven ability to collaborate with external vendors on critical infrastructure. This role offers the opportunity to lead transformative data center projects with high visibility and impact. If you are passionate about delivering cutting-edge infrastructure solutions, we encourage you to apply. Key Responsibilities Oversee building and MEP design, operation, and maintenance, including reviewing building and MEP drawings and proposals across all project phases. Lead operational activities for large-scale data center campuses, from early design phases through delivery and daily operation. Operate and maintain critical data center facilities and equipment, ensuring reliability and performance. Collaborate with external vendors to select, procure, and manage critical equipment, such as generators, UPS, chillers, and CDUs. Provide technical expertise on all aspects of data center building, equipment, and

At Snowflake, we are powering the era of the agentic enterprise. To usher in this new era, we seek AI-native thinkers across every function who are energized by the opportunity to reinvent how they work. You don’t just use tools; you possess an innate curiosity, treating AI as a high-trust collaborator that is core to how you solve problems and accelerate your impact. We look for low-ego individuals who thrive in dynamic and fast-moving environments and move with an experimental mindset — who rapidly test emerging capabilities to discover simpler, more powerful ways to deliver results. At Snowflake, your role isn't just to execute a function, but to help redefine the future of how work gets done. Build the future of the AI Data Cloud. Join the Snowflake Stellar Design System team. Snowflake Design is a world-class team of curious problem solvers on a mission to evolve and improve the way the world works with data. Great design is a strategic differentiator for Snowflake — but that differentiation doesn’t come automatically. We’re looking for talented, collaborative design engineers to join the team and drive the mission forward while doing career-defining work. As a Staff Design Engineer, you are the cornerstone of delivering the ultimate user experience. You will be entrusted with the highest level of polish, creativity, and interaction design, pushing the boundaries of what's possible in the most innovative areas of our product. This role offers the unique opportunity to have broad creative license, empowering you to lead and create groundbreaking systems and experiences that marry aesthetics with functionality, making data more accessible and actionable for our customers. WHAT YOU WILL DO: Embed with feature teams to up-level experiences Setting the front-end architecture vision, not just contributing to it Driving adoption and influencing teams outside your direct org Owning the technical roadmap for a system or component pillar Design and build exceptional expe