Design Verification Lead in India

Principal Engineer, Project Design Verification Lead — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers. You will lead our Bangalore-based CPU Core Design Verification team, driving both the technical strategy and the people leadership behind verification of our high-performance, out-of-order RISC-V CPUs. You will manage a team of core-level verification engineers, partner closely with our Santa Clara and Austin sites, and own delivery of core verification from architecture definition through tapeout readiness. This role is hybrid based out of Bangalore, India, with regular collaboration across our globally distributed CPU organization. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are 15+ years of CPU/DV experience, including 7+ years leading verification teams, with strong hands-on expertise in high-performance, out-of-order CPU verification. Deep microarchitecture & verification expertise, including ISA, RTL, UVM/CVM, testbench development, regressions, coverage, and complex debug. Strong people and technical leadership, with experience hiring, mentoring, developing engineers, and setting verification strategy and methodology across teams. Highly

Lead Principal Engineer, Design Verification — Hyderabad - Phoenix Aquila, India. Apply via Workday.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Senior Emulation Engineer Location: India - Remote Job Description: At EnCharge AI, we are building the next generation of AI compute silicon — purpose-built for high-performance, low-power, and scalable AI inference. As an Emulation Engineer, you will play a critical role in validating complex AI accelerator architectures on emulation platforms before tape-out. This position is ideal for someone passionate about bridging the gap between hardware and software in fast-paced, deep tech environments. Responsibilities: • Set up and maintain Siemens Veloce emulation and prototyping platforms • Adapt SoC designs for Emulation and Prototyping • Develop and debug emulation testbenches and system-level environments • Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation. • Collaborate with design and verification teams to isolate design issues and accelerate debug. • Optimize performance of the emulation workloads and reduce turnaround time. • Work with firmware/software teams to enable use of emulators for OS and driver testing. Required Background: • BS/MS/Ph.D. in EE, CS, or related field with 7+ years of SoC design experience. • Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based prototyping systems (proFPGA, HAPS, or Protium) • Experience with emula

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a hands-on RTL Design Engineer to own the microarchitecture and RTL implementation of the Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller . You’ll collaborate with cross-functional teams—architecture, firmware, software, DV, and PD—to define, design, and optimize power management solutions for next-generation RISC-V/ARM-based SoCs. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels. During the interview process, you will beevaluated and offered a level that aligns with your experience, which may differ from the one in this posting. Who You Are 5–10 years of experience in ASIC/SOC/IP design, with hands-on experience in microarchitecture and RTL development Skilled in Verilog/SystemVerilog and comfortable working across design, debug, and analysis Design and develop microarchitectures for a set of highly configurable IPs Microarchitecture and RTL coding ensuring optimal performance, power, area Work with verification teams on assertions, test plans, debug, coverage, etc. Deep understanding of power management concepts—clocking, reset, DVFS, and low-power modes Familiar with RISC-V or ARM-based SoCs and standard bus protocols (AXI, AHB, APB, CHI) Awareness of functional safety (ISO 26262) practices in hardware design What We Need Abil

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs

Silicon Verification Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery. Responsibilities Verification planning, specification and closure of functional coverage Providing feedback to architects Test generation and failure diagnosis/triage Contributing to shared verification infrastructure Ensuring good communication between sites Essential skills: • Verification experience in relevant industry • Proven leadership and planning skills • Highly motivated, a self starter, and a team player • Ability to work across teams and programming languages to find root causes of deep and complex issues • Experience of the verification process applied in CPU and/or ASIC environments • System Verilog, Python, C++, Linux Desirable skills: • UVM • SVA • Assembly languages • LLVM, GCC • DVCS e.g. Git • SGE or other DRMS • XML and XPath/XSLT • Web programming – HTML/DOM, Javascript, SQL Benefits: In addition to a competitive salary, Graphcore offers a competitive benefit

Silicon Verification Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery. Responsibilities Verification planning, specification and closure of functional coverage Providing feedback to architects Test generation and failure diagnosis/triage Contributing to shared verification infrastructure Ensuring good communication between sites Essential skills: • Verification experience in relevant industry • Proven leadership and planning skills • Highly motivated, a self starter, and a team player • Ability to work across teams and programming languages to find root causes of deep and complex issues • Experience of the verification process applied in CPU and/or ASIC environments • System Verilog, Python, C++, Linux Desirable skills: • UVM • SVA • Assembly languages • LLVM, GCC • DVCS e.g. Git • SGE or other DRMS • XML and XPath/XSLT • Web programming – HTML/DOM, Javascript, SQL Benefits: In addition to a competitive salary, Graphcore offers a competitive benefit

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers.You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU verification or closely related digital design. You know high‑performance out‑of‑order CPU microarchitecture in depth. You work comfortably with RTL, waveforms, logs, and complex debug scenarios. You communicate clearly across design, DV, emulation, and post‑silicon teams. What We Need Plan and drive functional verification for CPU core features and complex microarchitectural scenarios. Develop UVM, assembly, and C/C++ based stimulus, functional models, and coverage for ISA, RISC-V extensions, and un-core components. Debug simulation and emulation regressions using RTL understanding, waveforms, and logs to identify and resolve issues efficiently. Build and enhance coverage models, testbenches, and debug infrastructure to improve verification quality and coverage closure. Collaborate with design, validation, and

About Us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Job Summary Working within the logical design team, the silicon logical design engineer is responsible for a wide range of logical design tasks. The team is responsible for delivering the Microarchitecture and RTL design to implement the chip architecture specification for Graphcore Silicon, working closely with other engineers within the Silicon team. The successful candidate will be responsible for helping the team deliver high quality micro-architecture and RTL for Graphcore chips, working within the logical design team and with the broader Silicon team to ensure we meet the company objectives for Silicon delivery. Responsibilities and Duties Integrate IP and subsystems into top-level SoC designs Develop and maintain build and configuration environments Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level Support verification and physical design teams through clean interface hand-offs Debug and resolve integration-related issues across multiple hierarchies Contribute to the continuous improvement of integration flows and automation Producing high quality microarchitecture and other documentation Ensure good communication between sites to maintain consistent working practises Candidate Profile Essential skills: Logical design experience in relevant industry Experience range 8-12 years in Semiconductor Industry/Product development exposure. Be highly motivated, a self-starter, and a team player Ability to work across teams and debugging issues seen to find root cau

About Us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Job Summary Working within the logical design team, the silicon logical design engineer is responsible for a wide range of logical design tasks. The team is responsible for delivering the Microarchitecture and RTL design to implement the chip architecture specification for Graphcore Silicon, working closely with other engineers within the Silicon team. The successful candidate will be responsible for helping the team deliver high quality micro-architecture and RTL for Graphcore chips, working within the logical design team and with the broader Silicon team to ensure we meet the company objectives for Silicon delivery. Responsibilities and Duties Integrate IP and subsystems into top-level SoC designs Develop and maintain build and configuration environments Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level Support verification and physical design teams through clean interface hand-offs Debug and resolve integration-related issues across multiple hierarchies Contribute to the continuous improvement of integration flows and automation Producing high quality microarchitecture and other documentation Ensure good communication between sites to maintain consistent working practises Candidate Profile Essential skills: Logical design experience in relevant industry Experience range 4-8 years in Semiconductor Industry/Product development exposure. Be highly motivated, a self-starter, and a team player Ability to work across teams and debugging issues seen to find root caus

About us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Job Summary Working within the Silicon verification team, the silicon verification engineer is responsible for a wide range of tasks within the silicon verification team. This person is responsible for verification activities within Graphcore, helping the silicon team meet the company objectives for quality silicon delivery. The Team The verification team sits within the Silicon design team. We are responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. Responsibilities and Duties V erification activit i es within the verification team Ensuring good communication between sites Verification planning, specification and closure of functional coverage Providing feedback to architects Test generation and failure diagnosis/triage Contributing to shared verification infrastructure Candidate Profile Essential: verification experience in relevant industry Proven leadership and planning skills Be highly motivated, a self starter, and a team player Ability to work across teams and programming languages to find root causes of deep and complex issues Ability to research along with the knowledge to solve complex problems Presents technical and functional knowledge to design experiments/ projects that contribute to overall

Silicon Physical Design Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, fo

NVIDIA is seeking a highly enthusiastic and motivated Verification Engineer to verify the design and implementation of the next generation of control subsystems for the world’s leading GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We are united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.” What you’ll be doing: As a key member of our ASIC Verification team, you will contribute to verifying graphics and compute features within an IP. You will be responsible for IP-level verification of GPU ASICs, including the design, architecture, golden models, and micro-architecture, using advanced verification tools and methodologies. You will work with the specifications, develop test plans, tests and verification infrastructure using UVM methodology and ensure functional and code coverage of all the RTL which you will verify. Work with HW architects and designers to make the right implementation choices. You will be working with architects, designers, and other members of yo

NK Securities Research is a leading financial firm that leverages cutting edge technology and sophisticated algorithms to trade the financial markets. Founded in 2011, we have gained invaluable experience in the field of High Frequency Trading across different asset classes. With a focus on innovation, entrepreneurship, and collaboration, we aim to foster a dynamic work environment that reflects a startup culture. Role Overview As an FPGA Developer, you will design, implement, and rigorously test RTL (Register-Transfer Level) designs to power our high-frequency trading strategies. Your contributions will play a pivotal role in reducing system latency and enhancing performance, directly impacting trading outcomes. Key Responsibilities Design and Implementation: Develop high-performance RTL designs using VHDL or Verilog for FPGA-based systems. Optimize hardware implementations for ultra-low latency and high throughput. Testing and Debugging: Perform thorough functional and timing testing of RTL designs, ensuring adherence to specifications. Debug and resolve issues using FPGA debugging tools such as SignalTap, ChipScope, or ModelSim. Collaboration and Documentation: Work closely with hardware and software teams to ensure seamless integration of FPGA solutions with the Software Trading Stack. Maintain clear and comprehensive documentation of designs, test cases, results and benchmarks Qualifications Technical Skills: RTL Development: Strong fundamentals in digital logic design, Boolean algebra, FSMs and synchronous design. Proficiency in VHDL or Verilog/SystemVerilog, with a strong focus on efficient and optimized designs. FPGA Tools: Hands-on experience with industry-standard tools such as Xilinx Vivado. Testing and Verification: Expertise in writing testbenches and conducting simulation-based verification. Familiarity with static timing analysis and achieving timing closure. Familiar with CocoTB or any similar testing setup. Debugging: Proficiency in GHDL synthesis a