Intern Design Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we are transforming how the world uses information to enrich life. The High Bandwidth Memory (HBM) Design team develops industry-leading memory solutions that enable advances in Artificial Intelligence, high-performance computing, graphics, and data-center applications. Our engineers collaborate across global teams to deliver innovative memory architectures and semiconductor technologies that power next-generation computing systems. As an HBM Design Engineer Intern, you will work alongside experienced memory engineers and gain hands-on experience in semiconductor design, simulation, verification, and analysis. This internship provides exposure to industry-standard design methodologies, EDA tools, and cross-functional collaboration throughout the product development lifecycle. You will also have opportunities to apply AI-Assisted and AI-Enabled workflows to improve engineering productivity, debug efficiency, and design quality. Responsibilities Assist with the design, simulation, analysis, and verification of HBM memory and logic circuits using industry-standard semiconductor design tools. Support RTL development, circuit implementation, timing analysis, power analysis, and functional validation activities. Develop scripts, automation solutions, and AI-Assisted workflows to improve design productivity, debug efficiency, and design-flow quality. Collaborate with Design, Verification, Physical Design, CAD, and Product Engineering teams on technical reviews, debug activities, and project deliv

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we are transforming how the world uses information to enrich life. The High Bandwidth Memory (HBM) Design team develops industry-leading memory solutions that enable advances in Artificial Intelligence, high-performance computing, graphics, and data-center applications. Our engineers collaborate across global teams to deliver innovative memory architectures and semiconductor technologies that power next-generation computing systems. As an HBM Design Engineer Intern, you will work alongside experienced memory engineers and gain hands-on experience in semiconductor design, simulation, verification, and analysis. This internship provides exposure to industry-standard design methodologies, EDA tools, and cross-functional collaboration throughout the product development lifecycle. You will also have opportunities to apply AI-Assisted and AI-Enabled workflows to improve engineering productivity, debug efficiency, and design quality. Responsibilities Assist with the design, simulation, analysis, and verification of HBM memory and logic circuits using industry-standard semiconductor design tools. Support RTL development, circuit implementation, timing analysis, power analysis, and functional validation activities. Develop scripts, automation solutions, and AI-Assisted workflows to improve design productivity, debug efficiency, and design-flow quality. Collaborate with Design, Verification, Physical Design, CAD, and Product Engineering teams on technical reviews, debug activities, and project deliv

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron Technology’s DRAM and Emerging Memory Group (DEG) is a distributed team of engineers and innovators focused on advancing next-generation memory technologies. For more than 43 years, Micron has been a leader in semiconductor innovation, delivering solutions that power applications ranging from artificial intelligence and high-performance computing to immersive digital experiences. The team is committed to innovation, integrity, sustainability, and meaningful community impact while driving the future of memory technology. As an HBM Memory Design Engineer, you will design, analyze, and optimize digital, analog, and memory circuits used in High Bandwidth Memory (HBM) products. You will collaborate with global design, verification, and product teams to develop high-performance DRAM solutions that meet manufacturability, reliability, and performance objectives. This role provides the opportunity to contribute to innovative memory technologies supporting AI, HPC, and data-centric applications. As part of Micron’s AI-Enabled workforce transformation, you will leverage AI-Assisted tools and data-driven methodologies to improve engineering productivity, accelerate design analysis, enhance decision-making, and drive innovation throughout the product development lifecycle. Responsibilities Design, analyze, and optimize memory, logic, and analog circuits for HBM products, including support for layout, validation, and tape-out activities. Perform circuit verification, parasitic modeling, and design simulations

Intern - DRAM Design Engineer — Boise, ID - Main Site. Apply via Workday.

Intern - DRAM Design Engineer — Boise, ID - Main Site. Apply via Workday.

Intern - DRAM Design Engineer — Boise, ID - Main Site. Apply via Workday.

DRAM Design Engineer (Intern) — Jalisco, Mexico. Apply via Workday.

DRAM Design Engineer (Intern) — Jalisco, Mexico. Apply via Workday.

Intern - Digital IP Design Engineer, DRAM — Boise, ID - Main Site. Apply via Workday.

By submitting your resume, you’re expressing interest in our 2027 RDSS (Research and Development Substitute Services) program. Please confirm your eligibility with the local district office before applying the role. NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU & SOC acts as the brains of computers, robots, and self-driving cars that can understand the world. We are looking for Design Validation Engineer in Taipei for board/system power qualification and function test, responsible for NVIDIA Data Center platform, Graphics board, ARM Based platform and Autonomous Driving Platform. If you're creative and autonomous, we want to hear from you! What you'll be doing: Server/Motherboard/Mobile system functionality test. Clock/Sequency/GPIO signal measurement and verification. WAT (wide area test) function test. Gaming test. High/Low speed interface SI test. Co-work with hardware design engineers on debug and FA. Co-work with mechanical/thermal engineers for cooler/heatsink design. What we need to see: Masters degree in EE, computer science, or relative majors. Proficient with Linux system and GPU setup. Capable of writing simple shell scripts and analyzing test results using commands. Familiar with PC and Datacenter system hardware assembly, MB BIOS upgrade, and network troubleshooting Proficient with a programming language (C/C++, Python, Java, or Perl) Understand UEFI boot OS startup process and out-of-band (

Intern - HBM SoC RTL Design Engineer — Folsom, CA. Apply via Workday.

Intern - DRAM IP Circuits Design Engineer — Boise, ID - Main Site. Apply via Workday.

By submitting your resume, you’re expressing interest in our 2027 RDSS (Research and Development Substitute Services) program. Please confirm your eligibility with the local district office before applying the role. NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. With the continuous improvement of chip technology, design scale and performance/power ratio, the physical design of digital chips is facing outstanding challenges in high frequency, low power consumption and multiple applications. High efficiency, high quality of the implementation of the construction chip is the guarantee of the company's competitiveness. As an ASIC-PD engineer at NVIDIA, you'll be responsible for the stage from RTL frozen to tape out, include synthesis, formal verification, constraints definition, timing closure/sign off, study on the timing impact of process and related methodology work. You will face the biggest challenge based on the most advanced process on building chips in the world. What you'll be doing: Chip integration and netlist generation Synthesis RTL/netlist quality check </li

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Design Technology Co-Optimization (DTCO) team works at the intersection of process technology, standard cell architecture, and design implementation to optimize power, performance, and area (PPA) for advanced memory products. The team collaborates closely with standard cell library, RTL, and physical design engineers to evaluate design tradeoffs and develop methodologies that improve silicon outcomes. As a DTCO Intern, you will gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level. You will use industry-standard place-and-route tools and AI-enabled automation techniques to implement, benchmark, and optimize logic blocks while developing practical skills in physical design, timing closure, and design analysis. Responsibilities Implement standard cell logic blocks using industry-standard physical design tools, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization activities focused on PPA assessment. Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations, identifying opportunities for improvement. Perform static timing analysis (STA), investigate setup and hold timing violations, and support timing closure activities. Execute physical verification checks, including DRC, LVS, and IR-drop analysis, and assist with resolving design issues. Leverage Generative AI, AI Assistants, and Agentic AI solutions to automate data collection, reporting, comparison, and w

Design Verification Engineer Intern — Jalisco, Mexico. Apply via Workday.