Implementation Associate in Austin

Mechanical and Thermal Laboratory Technician Position Summary Graphcore is a globally recognized leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data center hardware that provide the specialized processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin, which will play a central role in Graphcore's work building the future of AI computing. Responsibilities The Mechanical and Thermal Laboratory Technician is a hands-on technical role supporting the development and validation of advanced AI hardware systems for data center environments. Working as part of a cross-functional engineering team, this individual will be responsible for executing mechanical and thermal laboratory testing, supporting product validation activities, prototype fabrication and assisting with troubleshooting and root-cause analysis of complex hardware systems. Requirements Associate degree in Mechanical Engineering Technology or a related technical field preferred. Equivalent combinations of education, training, and relevant experience will be considered, including experienced non-degreed candidates or candidates with degrees in unrelated disciplines. Minimum of 5 years of experience working in mechanical laboratories, machine shops, test labs, or similar technical environments. Experience with server hardware platforms and data center equipment. Knowledge of Direct Liquid Cooling (DLC) systems and their implementation in server environments. Experience operating forklifts, pallet jacks, and other material-handling equipment. Key Responsibilities Execute mechanical and thermal test plans to validate hardware designs a

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking an experienced Project Manager to lead our ERP implementation and drive delivery across technical and business teams. In this role, you will bridge Solution Architects with stakeholders across Sales, Supply Chain, Finance, Trade, Infosec, and Engineering to keep the program aligned, accountable, and moving forward. This role is hybrid, based out of Santa Clara, CA, or Austin, TX. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An experienced project manager who has led complex ERP implementations, such as NetSuite or SAP. Skilled in project management methodologies and tools, including Jira and Asana. A strong interpersonal communicator who can influence, align, and mediate across technical and business teams. Able to synthesize complex technical discussions into clear, actionable reporting for varied stakeholders. What We Need Define project scope, milestones, deliverables, and governance for the ERP implementation. Manage external consultants, monitor adherence to statements of work, and drive accountability for delivery. Coordinate Sales, Supply Chain, Finance, Trade, Infosec, Engineering, Solution Architecture, and o

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team and lead the front-end RTL physical implementation team. Drive CAD flows on multiple process technologies while working closely with core micro-architects to refine CPU core configurations and optimizing PPA. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, RTL and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An expert in physical design practices used to optimize PPA Experienced in high-performance physical design. Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis. Skilled in synthesis, place and route tools including flows and physical design methodology. Background in CPU micro-architecture. What We Need Own front‑end physical implementation and PPA definition for a high‑performance RISC‑V CPU and CPU subsystem Work closely with microarchitects and RTL designers to “make the IP better” by optimizing frequency, power, and area

Hyliion is committed to creating innovative solutions that enable clean, flexible and affordable electricity production. The Company’s primary focus is to develop distributed power generators that can operate on various fuel sources to future-proof against an ever-changing energy economy. Job Purpose The Advanced Engineer, Power System Controls plays a key role in the design, development, and implementation of control software for Hyliion’s Karno Power Module. This position focuses on systems involving combustion, thermal management, pressure regulation, high-voltage, and power management. The engineer will be responsible for developing and validating control algorithms, tuning system parameters, and analyzing data to ensure performance meets engineering specifications. Additional responsibilities include preparing technical documentation, supporting root cause analysis, and ensuring timely, high-quality software delivery. The role requires cross-functional collaboration and occasional travel to support system testing and troubleshooting. Duties and Responsibilities Design, develop, and implement high-quality control software for Hyliion’s Karno Power Module, which includes combustion, thermal, pressure, high-voltage and power management systems. Define and conduct tests to verify software and tune control parameters to meet key performance indicators. Prepare reports and technical documentation related to system performance, control strategies, and compliance. Process and analyze data to verify software against engineering specifications, support root cause analysis and for optimizing performance. Ensure on time delivery with quality. Assist product team in defining customer requirements and generate corresponding engineering specifications. Qualifications Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions. Qualifications include: Education, Experience and Cert

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid , based out of Austin, TX, Santa Clara, CA or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts. Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration. Strong problem solver who excels at debugging complex issues across design hierarchies. Collaborative team player who thrives in fast-paced, technically challenging environments. What We Need BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs. Expertise with industry-

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. The Director, Finance Systems will lead the strategy, architecture, implementation, and ongoing evolution of the systems and technology that enable Finance to operate effectively at scale. This leader will partner across Finance, Accounting, Tax, Treasury, Operations, IT, HR, and other business functions to build an integrated, automated, and data-driven Finance technology ecosystem - ensuring we are using the right tools and workflows, leveraging automation and AI where appropriate, to operate lean without sacrificing rigor. This role is ideal for a finance-minded technology leader who understands that great systems are not simply implementations—they are the foundation for scalable processes, reliable data, strong controls, faster decisions, and an increasingly AI-enabled Finance organization. This role is remote, based out of the United States or Toronto, ON. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring a deep understanding of finance and accounting processes, paired with expertise in technology, data, and systems. You are comfortable discussing financial close, revenue recognition, inventory accounting, and financial pla

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking talented Physical Design Engineers to implement high-performance partitions for an industry-leading AI SOC. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid, based out of Austin,TX or Santa Clara, CA or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are Experienced with synthesis and place-and-route flows, especially using Synopsys Design Compiler / Fusion Compiler and IC Compiler II. Comfortable in a small, cross-functional physical design team, owning a block or subsystem and partnering on tapeout milestones with clear communication and accountability. Ideally bring extra depth in areas such as UPF/multi-voltage power domains, SoC interface IP integration (e.g. I3C, UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementati

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent licenses RISC-V and AI IP to customers who need hardened, PPA-proven deliverables on their target node and foundry. This role owns physical implementation of those IP blocks end to end, from synthesis through PnR, timing closure, and GDSII signoff, and directly determines how fast we can commit to a customer's timeline. This role is hybrid, based out of Toronto, ON; Austin, TX; or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on physical design engineer who owns blocks end to end, with a track record of block-level and IP tapeouts on advanced nodes. Driven by PPA outcomes, working closely with RTL owners to close critical paths and hit power budgets. Rigorous about signoff quality, because our IP ships to customers who integrate it without you in the room. What We Need BS/MS/PhD in EE/ECE/CE/CS with 5+ years of block-level or IP-centric physical design through tapeout. Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl). Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage sc

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a talented Physical Design Engineer to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid, based out of Austin, TX or Santa Clara, CA or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts. Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration. Strong problem solver who excels at debugging complex issues across design hierarchies. Collaborative team player who thrives in fast-paced, technically challenging environments. What We Need BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs. Expertise with industry-stan

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an exceptional Senior-level Physical Design Engineer to drive top-level implementation of our complex AI and CPU System-on-Chip designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned physical design engineer who thrives on complex, full-chip implementation challenges. Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams. Passionate about optimizing chip-level implementations for power, performance, and area. Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules. What We Need 8+ years of top-level SOC physical design experience on complex, multi-million gate designs. Deep expertise in hierarchic

Principal Embedded SW/FW Engineer (Bringup) - Austin, Tx, USA Job Summary We have an exciting opportunity to be part of a collaborative, cross-functional development team validating cutting-edge, high-performance AI chips and platforms. You will play a key role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to provide technical guidance to other engineering team members. In this role, you can leverage our experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. The Team The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team. Responsibilities and Duties Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon Deploy silicon validation tests on first silicon and debugging them Develop automated test framework and regression test suites in Python to optimize validation efficiency Collaborate closely with engineers from many other disciplines on a variety of topics Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies Analyse test results, identify and debug failures/defects Contribute to shared test and validation infrastructure Provide feedback to architects Candidate Profile Essential: Understanding of ML

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives, spanning AI research specialists, silicon designers, software engineers and systems architects. Job Summary We are looking for an experienced Principal Engineer to join our System Management team and help lead the development of critical interfaces used by internal and external customers to manage system state. You will provide technical leadership within assigned areas of System Management, guide architecture and implementation choices, mentor engineers and translate broader technical direction into effective execution. This is a hands-on engineering role for someone who can lead complex technical work, improve reliability and operational readiness, and collaborate effectively across multiple engineering disciplines. The Team The System Management team sits within the Software Platform group and helps build Graphcore products into large-scale AI solutions for our customers. The team is responsible for developing the interfaces between hardware, AI software and frameworks, as well as providing interfaces for public and private cloud environments. This includes system management capabilities that abstract complex hardware administration and enable reliable deployment and operation at scale. As one of the first teams to work with new hardware and software, we regularly solve complex system-level problems

At Snowflake, we are powering the era of the agentic enterprise. To usher in this new era, we seek AI-native thinkers across every function who are energized by the opportunity to reinvent how they work. You don’t just use tools; you possess an innate curiosity, treating AI as a high-trust collaborator that is core to how you solve problems and accelerate your impact. We look for low-ego individuals who thrive in dynamic and fast-moving environments and move with an experimental mindset — who rapidly test emerging capabilities to discover simpler, more powerful ways to deliver results. At Snowflake, your role isn't just to execute a function, but to help redefine the future of how work gets done. We are hiring a Senior Technical Architect for our Services Delivery team. Our SD organization partners with customers across every stage of their data and AI journey, from initial implementation through long-term platform strategy. In this role, you will own the technical delivery and outcome for complex, high-priority engagements, serve as the most senior technical voice in the room, and shape how our customers use Snowflake to drive real business transformation. AS A SENIOR TECHNICAL ARCHITECT AT SNOWFLAKE, YOU WILL: Customer Leadership and Advisory Lead customer engagements as the primary technical authority, owning architecture decisions and driving measurable outcomes across complex, multi-workstream implementations Partner with customer executives and senior technical leadership to define platform strategy, develop long-term roadmaps, and align Snowflake capabilities to business objectives Translate ambiguous business problems into well-defined, scalable technical solutions, with clear delivery paths and risk-mitigation strategies Serve as the trusted escalation point for technical challenges within engagements, unblocking delivery teams and resolving architectural issues Technical Architecture and Delivery Architect and implement end-to-end AI/ML solutions on Snowfl

About DevRev At DevRev, we're building the future of work with Computer – your AI teammate. Unlike traditional tools, Computer unifies all your data sources, tools, and workflows into a single AI-ready platform, giving employees real-time insights, proactive suggestions, and powerful agentic actions. It extends your existing software with AI-native apps and agents that work alongside your teams and customers – updating workflows, coordinating across teams, and eliminating repetitive work. We call this Team Intelligence: human-AI collaboration that breaks down silos, brings people back together, and frees you to solve bigger problems. Backed by Khosla Ventures and Mayfield with $150M+ raised, DevRev is trusted by global companies across industries. About the team The Applied AI Engineering team ensures our customers get the optimal experience from DevRev. As customers go through their DevRev journey, they may identify needs for integration with existing enterprise systems and services, workflow and process automation, or customization of the DevRev platform to achieve their business objectives. Our team works with customers to understand requirements and design, develop, and implement solutions to meet customer goals. Your mission is to systematically help customers find value with DevRev by developing a thorough understanding of their needs, owning coordination between internal and external stakeholders, and engineering the solution to get the job done. You are a product expert and will use your application development and AI/ML skills to ensure our customers get the most out of the DevRev platform. About the role As a Forward Deployed Architect, you will serve as a hands-on senior technical architect on the Applied AI Engineering team, owning the end-to-end design and delivery of AI-driven business transformation projects. You will work closely with pre-sales teams to scope technical integration and implementation strategies, translating business requirement

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to drive infrastructure for performance analysis, correlation and verification. You’ll work on a CPU based on RISC-V ISA, collaborating with core architects and RTL teams to deliver a highly efficient and performant design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Strong problem solver who can identify complex issues, develop practical solutions, and drive them through implementation. Enjoy building tools and improving the infrastructure, workflows, and methodologies that make CPU development more efficient. Skilled in C++ and Python, with experience using industry-standard compilation, simulation, and emulation tools. Experience with verification infrastructure and methodologies along with knowledge of high-performance CPU architecture and microarchitecture. Proficient in debugging RTL and logic across multiple design hierarchies and pre-silicon environments. What We Need Join a team driving improvements in CPU microarchitecture, verifying performance, and correlating results between RTL and the performance mode