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Silicon Physical Design Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, fo

Job Details: Job Description: We are looking for a PERC Runset Development Engineer to develop and Validate PERC (Programmable Electrical Rule Checker) rule decks. The role involves working closely with PDK Team and foundry to implement PERC and ensure design compliance. Key Responsibilities: • Rule Development: Develop, validate, and maintain complex PERC rule decks to identify electrical reliability violations (e.g., ESD paths, current density, voltage stress, and floating gates). • Multi-Tool Integration: Develop and optimize verification flows across multiple EDA environments, ensuring consistency in results between Calibre PERC( preferred), Cadence Pegasus, and Synopsys tools. • Cross-Functional Collaboration: Work closely with Device Physicists, Process Integration Engineers, and Analog Designers to translate reliability requirements into programmable rules. • Debug and Analysis: Provide expert-level support to design teams in debugging PERC violations, distinguishing between true reliability risks and tool-induced false positives. • Automation: Develop scripts (Python, SKILL, Tcl, or Perl) to automate the execution, reporting, and tracking of reliability checks across different design versions. • Documentation: Maintain detailed documentation of reliability check-sets and create guidelines for designers to implement correct-by-construction layouts. Qualifications: Required Skills: • Experience with PERC rule development (preferably using Calibre PERC). • Knowledge of ESD, latch-up and reliability verification. • Familiarity with SVRF, TVF, Python or Tcl scripting. • Strong debugging and problem-solving skills. • Knowledge of Linux and scripting (Python/Shell/Tcl) is desirable. • Experience with advanced technology nodes is an advantage. • Team player and be able to work with globa