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Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a Senior Accounts Payable Analyst to drive accurate, efficient AP operations and solve complex finance challenges. You’ll own AP quality, reconciliations, payments, and month-end activities while partnering across Finance and Procurement. Help us build smarter, scalable AP processes through automation, ERP, and AI-enabled workflows. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are 4+ years of Accounts Payable experience, ideally in a shared services/GCC environment, with strong exposure to PO/non-PO invoices, vendor reconciliations, AP aging and payment support. B.Com/BBA/BBM Finance or equivalent; M.Com, MBA Finance, CA Inter or CMA Inter is a plus. Strong attention to detail, ownership, communication skills and a solid understanding of AP controls, GST/TDS, payment terms and audit requirements. What We Need Own day-to-day AP quality control, review invoices and coding, resolve complex exceptions, blocked invoices, PO mismatches and vendor account discrepancies. Support payment proposals, AP aging, vendor reconciliations and month-end close while maintaining strong maker-ch

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking an experienced and motivated System IP RTL Design Lead to drive the definition and implementation of complex datacenter class IP for our next-generation semiconductor products. The ideal candidate possesses a deep understanding of System IP and SoC architecture, IP integration challenges, and is adept at leading a design team to deliver high-quality, scalable IP solutions. This role requires strong hands-on technical leadership, excellent communication skills, and a proven track record in the successful delivery of silicon IP. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned IP / SoC design leader with 20+ yrs of strong expertise in complex SoC architectures, high-speed protocols, and large-scale IP integration. Skilled in RTL design and debug (Verilog/SystemVerilog) with hands-on experience using industry-standard tools for simulation, synthesis, lint, CDC, and power analysis on high-frequency designs. Experienced in driving microarchitecture decisions, authoring design specifications, and performing complex PPA trade-off optimizations. A proactive problem so

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a hands-on RTL Design Engineer to own the microarchitecture and RTL implementation of the Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller . You’ll collaborate with cross-functional teams—architecture, firmware, software, DV, and PD—to define, design, and optimize power management solutions for next-generation RISC-V/ARM-based SoCs. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels. During the interview process, you will beevaluated and offered a level that aligns with your experience, which may differ from the one in this posting. Who You Are 5–10 years of experience in ASIC/SOC/IP design, with hands-on experience in microarchitecture and RTL development Skilled in Verilog/SystemVerilog and comfortable working across design, debug, and analysis Design and develop microarchitectures for a set of highly configurable IPs Microarchitecture and RTL coding ensuring optimal performance, power, area Work with verification teams on assertions, test plans, debug, coverage, etc. Deep understanding of power management concepts—clocking, reset, DVFS, and low-power modes Familiar with RISC-V or ARM-based SoCs and standard bus protocols (AXI, AHB, APB, CHI) Awareness of functional safety (ISO 26262) practices in hardware design What We Need Abil

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers.You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU verification or closely related digital design. You know high‑performance out‑of‑order CPU microarchitecture in depth. You work comfortably with RTL, waveforms, logs, and complex debug scenarios. You communicate clearly across design, DV, emulation, and post‑silicon teams. What We Need Plan and drive functional verification for CPU core features and complex microarchitectural scenarios. Develop UVM, assembly, and C/C++ based stimulus, functional models, and coverage for ISA, RISC-V extensions, and un-core components. Debug simulation and emulation regressions using RTL understanding, waveforms, and logs to identify and resolve issues efficiently. Build and enhance coverage models, testbenches, and debug infrastructure to improve verification quality and coverage closure. Collaborate with design, validation, and

📍 Location: Remote (Work from Home – India) 🕒 Experience: 2+ Years 💼 Employment Type: Full-Time About MeltPlan MeltPlan is an AI-native preconstruction platform transforming the way construction teams estimate, plan, and bid. By combining cutting-edge AI with experienced preconstruction professionals, we help General Contractors and Trade Contractors across the United States deliver faster, more accurate quantity takeoffs, identify scope gaps, and improve bid quality. Our mission is to modernize preconstruction through intelligent workflows that bring Code, Schedule, Scope, and Value together—enabling construction teams to make better preconstruction decisions with confidence. If you're passionate about construction estimating and want to work on real US projects while leveraging the latest AI-powered tools, MeltPlan is the place to grow your career. Position Overview We are looking for a detail-oriented Estimator with experience in US Construction Quantity Takeoffs . The ideal candidate should have strong expertise in Grading, Site Utilities, Concrete, and Rebar while also possessing a good understanding of other CSI divisions and overall project scope. Key Responsibilities Prepare accurate quantity takeoffs from construction drawings. Perform detailed takeoffs for: Grading Site Utilities Concrete Reinforcement (Rebar) Review architectural, structural, civil, and specification documents. Identify missing scope, drawing discrepancies, and RFI items. Prepare BOQs and quantity summaries. Coordinate with the preconstruction team to meet bid deadlines. Maintain high accuracy and quality across all takeoff deliverables. Support multi-trade quantity takeoffs when required. Required Qualifications Minimum 2 years of experience in US Construction Estimation/Quantity Takeoffs . Strong hands-on experience with: Grading Site Utilities Concrete Rebar Good understanding of CSI Divisions and overall construction scope. Ability to read and interpret civil, structural, and archi

Graphcore Senior Principal AI SoC Validation (Bring-up lead) Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. We are developing the next generation of AI compute, a large-scale system-on-chip (SoC) designed to power future high-performance AI systems. As the SoC Validation Lead, you will be responsible for enabling pre-production software to run reliably on new silicon quickly and efficiently, before showing that the silicon meets the highest standards of quality, reliability and functionality, ready for production deployment. You will lead a team delivering post-silicon validation across the full AI SoC, working across silicon, firmware, and platform levels. The role requires a deep technical understanding, strong hands-on debug experience, and the ability to collaborate effectively with hardware, software, and systems engineering teams. Key responsibilities Define and lead post-silicon validation strategy Develop and refine the overall post-silicon validation approach for our AI SoCs, ensuring reliable and timely delivery of validated silicon, architectural correctness, feature robustness, and at-scale system reliability. Drive cross-domain debug and issue resolution Lead investigation and resolution of complex issues spanning silicon, firmware, operating systems, and platform interactions. Ensure that fixes are effective and sustainable. Promote collaboration and shared understanding Work closely with

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. About the Role We are looking for Staff System Software Engineer in Test to join our team. In this role, you will be responsible for design, development, automation and reporting of Integration and system tests spanning across firmware and device drivers. This role requires you to have significant technical breadth and deep understanding of low-level system software specifically in server class systems. You will be part of a new team responsible for integration of different system software deliverables and development of system tests spanning all the components. You will contribute to shaping the test strategy , guide best practices and solve complex problems while maintaining a strong hands-on focus. You will partner with development and other QA teams to deliver high quality scalable and reliable solutions. About the Team Integration and system test team is responsible for verification and validation of integrated components across Board management controller (BMC), Firmware and Linux device driver. The team is also responsible for management and maintenance of common tools and pipel

Silicon Verification Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery. Responsibilities Verification planning, specification and closure of functional coverage Providing feedback to architects Test generation and failure diagnosis/triage Contributing to shared verification infrastructure Ensuring good communication between sites Essential skills: • Verification experience in relevant industry • Proven leadership and planning skills • Highly motivated, a self starter, and a team player • Ability to work across teams and programming languages to find root causes of deep and complex issues • Experience of the verification process applied in CPU and/or ASIC environments • System Verilog, Python, C++, Linux Desirable skills: • UVM • SVA • Assembly languages • LLVM, GCC • DVCS e.g. Git • SGE or other DRMS • XML and XPath/XSLT • Web programming – HTML/DOM, Javascript, SQL Benefits: In addition to a competitive salary, Graphcore offers a competitive benefit

Principal Embedded SW/FW Engineer (Bringup) - Bengaluru, multiple vacancies Job Summary We have an exciting opportunity to be part of a collaborative, cross-functional development team validating cutting-edge, high-performance AI chips and platforms. You will play a key role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to provide technical guidance to other engineering team members. In this role, you can leverage our experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. The Team The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team. Responsibilities and Duties Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon Deploy silicon validation tests on first silicon and debugging them Develop automated test framework and regression test suites in Python to optimize validation efficiency Collaborate closely with engineers from many other disciplines on a variety of topics Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies Analyse test results, identify and debug failures/defects Contribute to shared test and validation infrastructure Provide feedback to architects Candidate Profile Essential:

Staff Embedded SW/FW Engineer (Bringup) Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. Job Summary We have an exciting opportunity to be part of a collaborative, cross-functional development team developing C code used to validate cutting-edge, high-performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Bringup team, you will be involved with bringing first silicon to life, developing code primarily in C to configure and exercise systems and sub-systems on new silicon devices, and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. The Team The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team. Respons

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs

About us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Job Summary Working within the Silicon verification team, the silicon verification engineer is responsible for a wide range of tasks within the silicon verification team. This person is responsible for verification activities within Graphcore, helping the silicon team meet the company objectives for quality silicon delivery. The Team The verification team sits within the Silicon design team. We are responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. Responsibilities and Duties V erification activit i es within the verification team Ensuring good communication between sites Verification planning, specification and closure of functional coverage Providing feedback to architects Test generation and failure diagnosis/triage Contributing to shared verification infrastructure Candidate Profile Essential: verification experience in relevant industry Proven leadership and planning skills Be highly motivated, a self starter, and a team player Ability to work across teams and programming languages to find root causes of deep and complex issues Ability to research along with the knowledge to solve complex problems Presents technical and functional knowledge to design experiments/ projects that contribute to overall

Silicon Verification Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery. Responsibilities Verification planning, specification and closure of functional coverage Providing feedback to architects Test generation and failure diagnosis/triage Contributing to shared verification infrastructure Ensuring good communication between sites Essential skills: • Verification experience in relevant industry • Proven leadership and planning skills • Highly motivated, a self starter, and a team player • Ability to work across teams and programming languages to find root causes of deep and complex issues • Experience of the verification process applied in CPU and/or ASIC environments • System Verilog, Python, C++, Linux Desirable skills: • UVM • SVA • Assembly languages • LLVM, GCC • DVCS e.g. Git • SGE or other DRMS • XML and XPath/XSLT • Web programming – HTML/DOM, Javascript, SQL Benefits: In addition to a competitive salary, Graphcore offers a competitive benefit

Silicon Physical Design Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, fo

Location This is a hybrid role based out of our Gurugram office; 3 days in the office, 2 days remote. About Us Sauce Labs is the world’s largest full-lifecycle, test automation platform, and the company behind Selenium. Trusted by 80% of the world’s top ten largest financial institutions and over 300,000 enterprise users, Sauce Labs provides the only AI platform capable of turning business intent into autonomous testing and quality assurance. With a proprietary dataset of 8.7 billion test runs, Sauce Labs empowers the Fortune 2000 to bridge the gap between AI-driven code generation and enterprise-grade software quality. Learn more at http://saucelabs.com . Release Assurance at the Speed of AI | Meet the new Sauce Labs The Role We are seeking a proactive and detail-oriented HR Ops Manager to drive operational excellence and manage core employee lifecycle processes in our India office. In this role, you will be responsible for end-to-end Onboarding and Off-boarding, leading the Internal Committee for PoSH compliance, ensuring Indian statutory compliance, and supporting HRBP activities. Responsibilities 1. Onboarding & Offboarding Lifecycle Onboarding: Own the entire new-hire experience from offer acceptance to day 30/60/90 integration - ensuring document verification, background checks (BGV), system access, and orientation. Offboarding: Manage seamless exit processes, including resignation handling, exit interviews, asset clearance coordination, full & final (F&F) settlement coordination, and exit analytics. Continuously refine onboarding and offboarding workflows to improve candidate experience and operational efficiency. 2. PoSH Committee Management & Employee Relations Serve as the primary lead/Presiding Officer/member for the Prevention of Sexual Harassment (PoSH) Internal Committee (IC) . Ensure 100% compliance with the Indian PoSH Act, including organizing mandatory awareness sessions, annual filing, and managing IC meetings. Handle s