←Jobiba.Me
I
Active1mo ago

Analog Design Flow and Infrastructure Design Automation Manager

IntelĀ·šŸ“ Bangalore, India

Employment

Full-Time

Work mode

On-site

Experience

SENIOR LEVEL

Salary

Not disclosed

Salary not disclosed

Check market pay for comparable Analog Design Flow and Infrastructure Design Automation Manager roles before applying.

Salary →

Role overview

Job description

Job Details:

Job Description:

We are seeking an experienced Analog Design and Infrastructure DA Manager to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs..The ideal candidate combines deep analog/mixed-signal design flow and e-test structure development expertise with strong infrastructure leadership and disciplined configuration/data management practices. Key Responsibilities-1. Analog Design Environment and Flow Management-Own and maintain analog and mixed-signal design flows using platforms such as Virtuoso ,Develop and maintain schematic, layout, verification, and extraction flows (LVS, DRC).Support simulation environments including HSPICE, Corner analysis.Drive automation and methodology improvements to reduce turnaround time and increase design robustness. 2. Infrastructure and Compute Management Oversee Linux-based DA infrastructure including compute farms, storage systems, and license servers (FlexLM). Manage LSF/grid environments and job scheduling systems. Ensure scalability, system monitoring, high availability, and performance optimization. Partner with IT on hardware lifecycle planning, cloud integration, and disaster recovery. Maintain secure, access-controlled design environments aligned with IP protection policies. 3. Design Data, Manifest and Configuration Management Design Data Governance Manage large-scale analog design libraries, hierarchical database structures, and technology libraries. Define backup, archival, and retention policies for tapeout-critical data. Implement data integrity validation and corruption prevention controls. Oversee distributed storage systems optimized for EDA workloads. Manifest and Tapeout Release Management Own creation and governance of tapeout manifests including: PDK Versions, Tool Versions, Extraction/Verification Decks, Simulation Models, Signoff Configurations Establish reproducible environment release frameworks for analog programs. Implement controlled qualification flows for tool/PDK upgrades prior to production rollout. Maintain environment snapshots to ensure reproducibility and post-silicon traceability. Support formal tapeout readiness and design signoff reviews. Version Control and Configuration Management Deploy and manage version control systems (Git, Cliosoft, SVN, Perforce,) for: CAD scripts and automation, Methodology flows, PDK overlays, Verification decks Define branching, tagging, and release strategies for multi-project and multi-node environments. Implement dependency tracking across tools, PDKs, IP, and infrastructure. Apply infrastructure-as-code principles where applicable. Automation and Traceability Develop automated environment capture tools to log tool versions, library states, and system configurations. Enable reproducible simulations and environment packaging. Create dashboards and reporting metrics for design data health and DA service KPIs. 4. Leadership and Cross-Functional Collaboration Lead and mentor DA and infrastructure engineers. Serve as the primary interface between analog design, digital CAD, IT, and EDA vendors. Drive tool evaluations, upgrades, and vendor negotiations. Develop internal documentation, training programs, and best practices. Establish measurable service-level KPIs and continuously improve DA operations.

Qualifications:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 10+ years of experience in analog/mixed-signal design or CAD support. 5+ years of leadership experience. Strong hands-on experience with analog design platforms such as Virtuoso and p-cell development. Custom Compiler. Deep understanding of analog layout, verification flows, PDK integration, and tapeout processes. Proven experience managing design data governance and tapeout manifest control. Strong Linux system administration and scripting skills (Python, Tcl, Shell, SKILL). Experience with compute grid management, storage architecture, and license management. Expertise in version control and configuration management systems Preferred Qualifications Experience with advanced nodes (FinFET, GAA). Knowledge of CI/CD practices applied to EDA environments. Experience supporting geographically distributed design teams

Ā  Ā  Ā  Ā  Ā Ā 

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

What they are looking for

Skills & requirements

Qualification

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field; 10+ years of experience in analog/mixed-signal design or CAD support

I

Hiring company

Intel

Explore this employer's active roles, salary signals and company profile on Jobiba.

Keep exploring

Similar active roles

Fresh roles matched to this title and market.

View all →
I
šŸ“ Bangalore, India

Job Details: Job Description: We are looking for a PERC Runset Development Engineer to develop and Validate PERC (Programmable Electrical Rule Checker) rule decks. The role involves working closely with PDK Team and foundry to implement PERC and ensure design compliance. Key Responsibilities: • Rule Development: Develop, validate, and maintain complex PERC rule decks to identify electrical reliability violations (e.g., ESD paths, current density, voltage stress, and floating gates). • Multi-Tool Integration: Develop and optimize verification flows across multiple EDA environments, ensuring consistency in results between Calibre PERC( preferred), Cadence Pegasus, and Synopsys tools. • Cross-Functional Collaboration: Work closely with Device Physicists, Process Integration Engineers, and Analog Designers to translate reliability requirements into programmable rules. • Debug and Analysis: Provide expert-level support to design teams in debugging PERC violations, distinguishing between true reliability risks and tool-induced false positives. • Automation: Develop scripts (Python, SKILL, Tcl, or Perl) to automate the execution, reporting, and tracking of reliability checks across different design versions. • Documentation: Maintain detailed documentation of reliability check-sets and create guidelines for designers to implement correct-by-construction layouts. Qualifications: Required Skills: • Experience with PERC rule development (preferably using Calibre PERC). • Knowledge of ESD, latch-up and reliability verification. • Familiarity with SVRF, TVF, Python or Tcl scripting. • Strong debugging and problem-solving skills. • Knowledge of Linux and scripting (Python/Shell/Tcl) is desirable. • Experience with advanced technology nodes is an advantage. • Team player and be able to work with globa

PythonLinuxAIRecruitment
G
šŸ“ Bengaluru, IndiaĀ· Full-time

Job Summary Reporting to the Memory Validation leadership team, the Senior Silicon DDR/HBM Validation Engineer will be responsible for the bring-up, validation, characterization and debug of advanced memory subsystems used in next-generation AI compute platforms. The role will focus on DDR and HBM technologies, working closely with silicon design, firmware, characterization, platform and systems teams to ensure robust memory subsystem functionality, performance and reliability. The successful candidate will take ownership of significant validation activities, contribute to debug and root-cause analysis efforts, and help improve validation methodologies, automation and infrastructure. The Team The Memory Validation team sits within the Validation organisation and is responsible for the bring-up, validation, characterization and debug of memory subsystems across Graphcore silicon and platform products. The team supports DDR and HBM validation activities throughout the product lifecycle, from first silicon through production readiness. Engineers work closely with architecture, RTL, firmware, characterization, systems and platform teams to ensure memory technologies meet functionality, performance, reliability and performance objectives. Responsibilities and Duties Execute validation and bring-up activities for DDR and HBM memory subsystems Verify memory bring-up software, firmware and scripts against defined project requirements Debug firmware, hardware and system-level issues and contribute to root-cause analysis activities Analyse system logs, validation data and characterization results to identify failures and performance issues Perform PHY characterization and analog-level analysis during stress testing and validation activities Develop and execute functional, stress, performance and corner-case validation tests Perform signal integrity, voltage, frequency and timing measurements using laboratory instrumentation Char

PythonAIGoExcel

šŸ”” Get job alerts

New Analog Design Flow and Infrastructure Design Automation Manager jobs in Bangalore, India, straight to your inbox.

No spam Ā· Unsubscribe anytime