Analog Layout Engineer

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. As a Principal/MTS Engineer, you will be an integral part of our HIG HBM Team in Hyderabad, India, responsible for designing and developing complex Application-Specific Integrated Circuits to meet our product's specifications and requirements for High Bandwidth Memories, working for intensive applications such as artificial intelligence and high performance computing solution. Your expertise will contribute to the successful realization of pioneering semiconductor products, enabling our company to maintain its competitive edge in the industry. Role and Responsibilities Must have a solid understanding of die design . This includes knowledge of various die components, their functions, and how they interact within the overall tool. Familiarity with the principles of die design is essential to create effective and efficient layouts. Industry Involvement : You actively participate in standards committees, representing Micron and staying informed about industry developments. Leading Project Layout Team : You lead the establishment and growth of a layout team to meet Micron’s global HBM layout requirements. Technical Expertis

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Own the development and physical implementation of critical analog, mixed‑signal, and custom digital blocks, including block‑level and full‑chip layout ownership. Lead layout implementation using AI‑assisted and automated workflows, applying copilot‑based assistants, agentic AI flows, and rule‑aware automation to accelerate placement, routing and optimization. Perform and automate layout verification activities, including DRC, LVS, Antenna, Yield, ESD, TOTEM, EM/IR and quality checks. Drive on‑time delivery of blocks and partition‑level layouts with predictable quality and risk prediction/mitigation plans. Develop and deploy AI‑enabled methodologies for Semi-automated floorplanning, parasitic estimation, layout consistency checks and best‑practice enforcement, repetitive layout task elimination via SKILL, Python, TCL or agent‑based flows. Demonstrate technical leadership in planning, area and cycle‑time estimation, delegation and execution. Guide and mentor engineers in Analog layout fundamentals, Automation‑first approach, Design‑for‑quality and design‑for‑yield practices Collaborate closely with Design, CAD, Verification, Reliability, and Program Management teams, clearly communicating technical risks, schedule impacts and any optimization opportunities. Drive continuous improvement by identifying manual bottlenecks and converting them into scalable automated flows. Job Requirements </

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Lead full-chip floor planning, integration, physical implementation, signoff, and tape-out execution. Drive layout implementation of complex analog, mixed-signal, memory, and high-speed interface designs. Own DRC, LVS, ERC, EMIR, reliability, and manufacturability closure. Define and scale layout methodologies, best practices, and execution frameworks. Leverage Artificial Intelligence, Machine Learning, and Agentic AI to improve layout productivity, design quality, automation, and faster decision-making. Drive automation initiatives using AI-assisted design, verification, debugging, and knowledge management solutions. Lead cross-functional and global teams, mentor engineers, and drive technical excellence. Qualifications B. Tech /M. Tech in Electrical Engineering, Electronics, VLSI, or related field. 15&#43; years of hands-on custom layout experience. Proven success leading full-chip programs from concept through silicon tape-out. Deep expertise in: Analog & Mixed-Signal Layout Memory & High-Speed Interface Layout Full-Chip Floor planning & Integration Signal Integrity, Power Integrity, EM/IR Physical Verification & Signoff Advanced Node Technologies (FinFET/GAA) Strong proficiency with Cadence Virtuoso, Calibre, StarRC, Totem, and related EDA tools. Proven experience leveraging <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Responsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells and full chip level. Perform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, quality check and documentation. Responsible for development of digital block layouts using auto placement and route tools Responsible for basic understanding of skill coding and automation Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/achievements in multiple project environment. Guide developing team members in their execution of Sub block-level layouts & review their work Contribute to effective project-management. Effectively communicating with Global engineering teams to assure the success of layout project. Responsible for the reducing the layout effort by using AI tools Qualification/Requirements 5 to 8-year experience in analog/custom layout design in advanced CMOS process. Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Should have hands on experience in creating layout of cr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Responsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells and full chip level. Perform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, quality check and documentation. Responsible for development of digital block layouts using auto placement and route tools Responsible for basic understanding of skill coding and automation Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/achievements in multiple project environment. Guide developing team members in their execution of Sub block-level layouts & review their work Contribute to effective project-management. Effectively communicating with Global engineering teams to assure the success of layout project. Responsible for the reducing the layout effort by using AI tools Qualification/Requirements 5 to 8-year experience in analog/custom layout design in advanced CMOS process. Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Should have hands on experience in creating layout of cr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Own and drive custom analog and mixed-signal layout for critical LPDDR PHY blocks, including Datapath, bias networks, IO front ends, and reference circuits, ensuring robust operation across PVT, low noise coupling, and high matching accuracy 3-12 years of solid hands-on experience in custom analog and high-speed layout design, with proven expertise in implementing and delivering critical analog blocks and LPDDR/high-speed interfaces at advanced technology nodes Lead high-speed LPDDR (LPDDRx) interface layout execution , solving complex signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes Architect and implement scalable array-based layout strategies for DQ/DQS byte lanes, CA lanes, and replica paths, ensuring strict symmetry, pitch matching, repeatability, and multi-channel scalability Drive integration of custom digital and mixed-signal blocks within the PHY (training logic, calibration engines, test/debug circuitry), ensuring optimal clocking, congestion management, and isolation from sensitive analog regions Lead layout-aware co-design with circuit teams , enabling early closure of timing, noise, IR, EM, and parasitic effects, and influencing design decisions from a layout perspective Establish robust power distribution, grounding, and isolation strategies , including guard rings, deep N-well usage, decoupling, and domain separation for