FPGA Developer

NK Securities Research is a leading financial firm that leverages cutting edge technology and sophisticated algorithms to trade the financial markets. Founded in 2011, we have gained invaluable experience in the field of High Frequency Trading across different asset classes. With a focus on innovation, entrepreneurship, and collaboration, we aim to foster a dynamic work environment that reflects a startup culture. Role Overview As an FPGA Developer, you will design, implement, and rigorously test RTL (Register-Transfer Level) designs to power our high-frequency trading strategies. Your contributions will play a pivotal role in reducing system latency and enhancing performance, directly impacting trading outcomes. Key Responsibilities Design and Implementation: Develop high-performance RTL designs using VHDL or Verilog for FPGA-based systems. Optimize hardware implementations for ultra-low latency and high throughput. Testing and Debugging: Perform thorough functional and timing testing of RTL designs, ensuring adherence to specifications. Debug and resolve issues using FPGA debugging tools such as SignalTap, ChipScope, or ModelSim. Collaboration and Documentation: Work closely with hardware and software teams to ensure seamless integration of FPGA solutions with the Software Trading Stack. Maintain clear and comprehensive documentation of designs, test cases, results and benchmarks Qualifications Technical Skills: RTL Development: Strong fundamentals in digital logic design, Boolean algebra, FSMs and synchronous design. Proficiency in VHDL or Verilog/SystemVerilog, with a strong focus on efficient and optimized designs. FPGA Tools: Hands-on experience with industry-standard tools such as Xilinx Vivado. Testing and Verification: Expertise in writing testbenches and conducting simulation-based verification. Familiarity with static timing analysis and achieving timing closure. Familiar with CocoTB or any similar testing setup. Debugging: Proficiency in GHDL synthesis a

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a CPU Verification Fellow to lead verification strategy and execution for next-generation RISC-V high-performance processors. This role requires deep CPU verification expertise, strong microarchitecture understanding, and the ability to guide large engineering teams from early design through tapeout and post-silicon validation. The ideal candidate has verified complex out-of-order, speculative, superscalar CPUs and can define scalable methodology across simulation, formal verification, emulation, FPGA, and silicon bring-up. This role is hybrid, based out of Santa Clara, CA or Austin, TX. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have deep experience verifying high-performance superscalar CPUs, ideally including out-of-order and speculative processors. You have strong knowledge of RISC-V architecture, including ISA compliance, privileged architecture, virtual memory, atomics, vector extensions, and memory model behavior. You are highly proficient in SystemVerilog, UVM, constrained-random verification, assertions, functional coverage, and advanced debug methodologies. You have hands-on experience with CPU refere

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Staff Digital Design Engineer to help define, build, and optimize high-performance IP and SoC architectures for next-gen AI and compute workloads. This role is ideal for engineers who thrive at the intersection of microarchitecture, RTL implementation, and performance-aware design. This role is hybrid, based out of Toronto, Ottawa, Boston, or Austin. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A digital design expert with a deep understanding of computer architecture and IP microarchitecture. Skilled in RTL development (Verilog/VHDL) and familiar with full ASIC flows. Comfortable optimizing for power, performance, and area (PPA) under aggressive design goals. A naturally collaborative and technical engineer — you thrive in spec definition, peer reviews, and team-wide planning. What We Need Architecture and RTL implementation of Tenstorrent’s custom IP blocks and SoC components. Performance-aware design decisions for compute, interconnect, or memory-heavy blocks. Occasional contributions to validation using emulation, FPGA prototyping, or UVM flows. Strong synthesis and timing closure awareness to support backend

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join Micron’s SSD Controller Engineering team, where we develop advanced memory and storage technologies that power cloud, AI, and enterprise computing. We work across global teams to deliver innovative, high-quality storage solutions that help transform information into intelligence and enrich life for all. As a Principal PCIe ASIC Application Engineer, you will lead validation efforts for next-generation SSD controller ASICs from development through production. This is a highly visible technical leadership role where you will drive validation strategy, solve complex system challenges, and collaborate with architecture, firmware, design verification, and product engineering teams to ensure successful product delivery. Responsibilities: Lead ASIC validation activities from pre-silicon FPGA development through product qualification and production release Develop and implement validation plans covering functional, performance, power, reliability, and system-level testing Perform post-silicon bring-up, debug, and root-cause analysis across PCIe, NVMe, DDR, NAND/ONFI, and firmware subsystems Build automation frameworks, validation tools, and test infrastructure to improve efficiency and coverage Provide technical leadership, mentor engineers, and drive teamwork across global multi-functional teams Minimum Qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field 10+ years o

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Security Firmware Engineer on Micron's enterprise SSD team, you will design and develop security features that protect next-generation storage products against evolving cybersecurity threats. You will architect and implement cryptography-based solutions — including data encryption, Root of Trust, Secure Boot, Device Attestation, and Self-Encrypting Devices (SED) — while leading the transition to post-quantum cryptography for future product generations. This role spans the full Security Development Lifecycle, from threat modeling and architecture through implementation, testing, and certification. You will work across SoC, FPGA, and simulation platforms and collaborate cross-functionally to deliver security solutions aligned with industry standards including OCP, TCG, NVMe, and PCIe. Responsibilities Design and develop security features for Micron enterprise SSDs, protecting against cybersecurity threats across the product lifecycle Architect, implement, and debug cryptography-based security solutions including data encryption, Root of Trust, Secure Boot and Update, Device Attestation, and Self-Encrypting Devices (SED) Lead the transition to post-quantum cryptography algorithms (LMS, ML-DSA, ML-KEM) for next-generation products Implement security protocols aligned with OCP, TCG, NVMe, and PCIe specifications Debug security firmware on SoC, FPGA, and simulation platforms using tools such as JTAG, memory dumps, and bus analyzers Dri

Neptune Medical, is an innovative, venture capital funded medical device startup headquartered in Burlingame, CA. We have already commercialized novel medical devices using our technology. Now the team at Neptune is building something truly unique: a fully flexible medical robot that enables doctors to reach deep into human anatomy. Triton Robotic Endoscopy will disrupt flexible endoscopy and set a new standard in outcomes for decades to come. TITLE : Senior/Staff Linux Software Engineer – Robotics Platform POSITION SUMMARY: The Senior/Staff Software Engineer is a key member of the software team who will be responsible for implementing a robust vision compute pipeline on a Linux platform and will actively work with the software and vision teams. As part of the software team responsible for the compute platform for the Triton robot, this candidate will be instrumental in the selection, evaluation and integration of the embedded Linux computers, FPGA bridges and high-speed SerDes links in the novel camera and display system. This member is expected to collaborate on and own parts of the vision software subsystem, helping build a robust and safe software while demonstrating the flexibility and enthusiasm to handle multiple responsibilities in a fast-paced and collaborative start-up environment. The ideal candidate will act with passion and intensity in a medical device start-up that is fast paced and collaborative and display the ability to perform to the requirements outlined below. For the right person, this position will be a tremendously exciting and career-defining opportunity, making core contributions to a genuinely new type of medical robotic platform. ROLES AND RESPONSIBILITIES: Design and implement the compute platform for the vision pipeline for the Triton robot. Evaluate and prototype solutions for the control and vision subsystems using different computers and GPUs, optimizing for latency, efficiency and robustness. Design, develop, docu