Front End Design Verification Engineer

Forward was founded in 2013 by four Stanford Ph.D.s, building the industry's first network digital twin: a mathematically accurate model of the production network. It's the foundation for autonomous networking, giving engineers and AI agents the ability to know the impact of every change before it touches production. That founding instinct still defines how we work. We're accurate and evidence-driven, relentless about clarity, and we'd rather be certain than comfortable, building a groundbreaking platform that transforms how teams run and secure networks across every major cloud and vendor environment. Global leaders like Goldman Sachs, PayPal, S&P Global, IBM, and Dell trust Forward, alongside fast-growing enterprises and government agencies, realizing an average of $14.2 million in annual benefits, according to IDC. Backed by top-tier investors, including A. Capital, Andreessen Horowitz, Goldman Sachs, MSD Partners, Omega Venture Partners, Section 32, and Threshold Ventures, and headquartered in Santa Clara, we're most proud of our team: curious people who'd rather build what doesn't exist than accept how things have always been done. Forward is looking for a Senior Director of Engineering to lead our Applications engineering organization. Reporting directly to the SVP of Engineering, you will own an organization of approximately 40 engineers across the US and India responsible for the customer-facing application layer of the Forward platform, spanning both backend and frontend. A significant majority of the organization is based in India, where we expect to continue growing. This is a broad engineering leadership role with end-to-end accountability for the organization: people, architecture, execution, quality, and delivery. You will lead through engineering managers and senior technical leaders while remaining close enough to the technology to review designs, challenge architectural decisions, and help teams navigate difficult technical problems. You w

Location Details: Santa Clara, CA At GoDaddy the future of work looks different for each team. Some teams work in the office full-time; others have a hybrid arrangement (they work remotely some days and in the office some days) and some work entirely remotely.​ This is an in-office position and you’ll be expected to work full-time in an office location, and therefore must live within commuting distance from your assigned office. You will work from this office beginning on your first day. Join our team Join GoDaddy's Global IT Support team as a Desktop Support Technician in our Santa Clara office, where you'll be the face of IT for employees who rely on technology to do their best work every day. In this hands-on, 100% on-site role, you'll provide walk-up and escalated technical support, troubleshooting hardware, software, workplace technology, and connectivity issues while delivering an exceptional customer experience.You'll collaborate closely with a globally distributed team of support professionals across North America, EMEA, and APAC, helping resolve both everyday technical requests and high-priority incidents in a fast-paced environment. Success in this role is driven as much by your communication, empathy, and problem-solving skills as your technical knowledge, making it an excellent opportunity for someone who enjoys helping people and learning new technologies.If you're passionate about customer service, curious about how technology works, and looking to grow your career in enterprise IT, we'd love to hear from you. What you'll get to do... Provide front-line technical support to employees by diagnosing and resolving hardware, software, operating system, peripheral, and account-related issues, ensuring minimal disruption to productivity. Manage and prioritize incidents and service requests through the IT ticketing system, taking ownership from initial intake through troubleshooting, resolution, and follow-up communication. Configure, deploy, maintain,

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Design Verification Engineer to contribute to the unit-level verification of our RISC-V CPU front end—including instruction fetch, branch prediction, and surrounding fetch control structures. As a key individual contributor within our front-end DV team, you will focus on building testbenches, generating stimulus, and developing checkers for complex microarchitectural scenarios. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Front-End Experience: Solid background verifying CPU front-end blocks—such as instruction fetch, branch predictors (BTB, TAGE, RAS), instruction caches/TLBs, or decode—using SystemVerilog, UVM, and C++. Unit-Level Focus: Hands-on experience building clean, controllable unit testbench environments with precise stimulus and checking. Reusable Design: Pragmatic approach to building transactors, predictors, and scoreboards that can be reused across verification levels. Collaborative Problem Solver: Comfortable working alongside RTL designers to trace and fix misspeculation, redirect, and edge-case fetch bugs. What We Need Unit-Level Verifica

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron is seeking a Senior Digital Design Engineer to contribute to the development of advanced DRAM digital and mixed-signal blocks. This role is responsible for RTL design, implementation, synthesis, timing analysis, power optimization, and design quality throughout the RTL-to-GDS flow. The engineer will collaborate with architecture, verification, and physical design teams to deliver high-performance, power-efficient designs that meet product specifications and PPA (Power, Performance, Area) objectives for next-generation memory products. Responsibilities Design, develop, and deliver RTL for complex DRAM digital and mixed-signal blocks, ensuring alignment with product specifications and performance targets. Perform front-end design quality checks including linting, CDC/RDC analysis, logic synthesis, timing constraint development, and timing closure activities. Collaborate with architecture, verification, and physical design teams to optimize power, performance, area (PPA), and overall design quality. Develop and maintain synthesis and timing constraints (SDC), analyze timing reports, and drive timing closure across multiple operating scenarios. Improve design methodologies, automation, and RTL-to-GDS flows to enhance development efficiency, design quality, and time-to-market. Minimum Qualifications Master’s degree in Electrical Engineering (or equivalent) with 4+ years of experience, or Bachelor’s degree with 5+ years

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron is seeking a Senior Digital Design Engineer to contribute to the development of advanced DRAM digital and mixed-signal blocks. This role is responsible for RTL design, implementation, synthesis, timing analysis, power optimization, and design quality throughout the RTL-to-GDS flow. The engineer will collaborate with architecture, verification, and physical design teams to deliver high-performance, power-efficient designs that meet product specifications and PPA (Power, Performance, Area) objectives for next-generation memory products. Responsibilities Design, develop, and deliver RTL for complex DRAM digital and mixed-signal blocks, ensuring alignment with product specifications and performance targets. Perform front-end design quality checks including linting, CDC/RDC analysis, logic synthesis, timing constraint development, and timing closure activities. Collaborate with architecture, verification, and physical design teams to optimize power, performance, area (PPA), and overall design quality. Develop and maintain synthesis and timing constraints (SDC), analyze timing reports, and drive timing closure across multiple operating scenarios. Improve design methodologies, automation, and RTL-to-GDS flows to enhance development efficiency, design quality, and time-to-market. Minimum Qualifications Master’s degree in Electrical Engineering (or equivalent) with 4+ years of experience, or Bachelor’s degree with 5+ years

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are building the next generation of solid‑state drive controllers at Micron, where cutting‑edge ASIC design meets high‑performance storage innovation. Our team works across the full silicon lifecycle, partnering closely with verification, physical design, and system teams to bring complex designs to life. If you enjoy solving deep technical challenges and collaborating with experts across disciplines, this is an exciting place to make an impact! In this role, you will play a key part in delivering advanced ASIC designs from concept through production silicon. You will define micro‑architectures, develop RTL, and ensure designs meet performance, timing, and quality goals. This position offers strong ownership, collaboration, and the opportunity to leverage modern AI‑assisted tools to improve engineering efficiency and quality. Responsibilities: Design, implement, and debug complex RTL logic and integrate IP into larger subsystems Support front-end design flow including lint, CDC, synthesis, and ECO activities Collaborate with SOC design, verification, STA, and physical design teams to deliver high-quality silicon Develop automation scripts to improve design efficiency and productivity Use AI-assisted tools to enhance debugging, documentation, and code quality Minimum Qualifications: MS in Electrical Engineering or equivalent e