Hardware Physicist

Staff Software Engineer - Sensing (SF Bay Area) San Francisco Bay Area Job Title: Staff Software Engineer Location: SF Bay Area About Canopy At Canopy, we build technology that helps make healthcare environments safer for the people delivering care. Our connected safety platform powers real-time communication, response coordination, and location intelligence across hospitals and complex care environments. We operate in high-trust, high-reliability environments where software quality, operational resilience, and customer experience matter deeply. Our engineering organization is scaling alongside our growth, and we are looking for a Staff Software Engineer who can help shape both our technical direction and the way we build. This is not simply a feature delivery role. This is a systems-thinking role for an experienced engineer who can drive architecture, influence engineering standards, and help scale a platform, organization, and culture simultaneously. The Role Canopy is seeking a Staff Software Engineer to develop our next-generation sensing data pipeline — building the “physical full stack” from firmware and edge algorithms to the backend and frontend services that power them. You will bridge physical hardware and cloud systems, applying physics-based modeling to solve complex sensing challenges at scale that are not possible with traditional products. This is a unique role within Canopy to translate hardware schematics and firmware design into products that work in harsh environments and result in life-saving outcomes. We care deeply about building highly automated development environments that accelerate our prototyping and verification cycles, ensuring our mission-critical systems are built faster, safer, and with greater precision. How to you will make 10X impact: Drive the development of next-generation hardware that will be in the hands of millions of healthcare professionals Design and implement robust firmware across Canopy devices; build and mainta

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum Packaging Modeling Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for thermal modeling and simulation of various packaging solutions from silicon redistribution layers to IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Thermal modeling and simulation of packaging hardware to understand how heat flows from silicon test chips through various heat spreader hardware - Manage the overall integration of the packaging hardware and enable co-design between relevant stakeholders - Work closely with mechanical designers to define heat spreaders for optimal performance - Deliver and disseminate design milestones to stakeholders - Communicate designs in presentations and relevant documentation - Stay current with the latest developments in packaging technology and design techniques by attending conferences and rea

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum Packaging Signal/Power Integrity (SI/PI) Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for modeling and simulation of various packaging solutions from silicon redistribution layers to IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Modeling and simulation of packaging hardware including redistribution layers (e.g., interposers, RDLs), IC substrates, and silicon testchip routing - Work closely with stakeholders to meet design requirements - requirements come from both theory and hardware teams. In some pathfinding projects, you will be asked to participate in creating requirements and novel packaging hardware. - System-level modelling and simulation; end-to-end simulations to ensure designs meet system-level requirements - Deliver and disseminate design milestones to stakeholders - Communicate designs in pr

NVIDIA is looking for a Systems & Software Engineer interested in building and running reliable large scale infrastructure platform services. In this role you will create and support automation that manages infrastructure, as part of our organization running EDA platforms atop of NVIDIA hardware. What you’ll be doing: Design, build, deploy, and run infrastructure services & manage the software life cycle in scope to meet our business goals Build and maintain automation to eliminate manual toil and scale output without scaling effort Participate in the definition of our internal facing service level objectives and error budgets as part of our overall observability strategy Practice sustainable blameless incident prevention and incident response while being a member of an on-call rotation Consult with and provide consultation for peer teams on systems design best practices What we need to see: BS degree in Computer Science or a related technical field involving coding (e.g., physics or mathematics) or equivalent experience Experience coding in Python and/or Go. Note : you must be able to produce code without AI assistance during the interview process. Experience with infrastructure automation and distributed systems design Experience developing tools for running large scale private or public cloud systems in production In depth knowledge of Linux systems and Containers A track record showing a good balance between initiating your own projects, convincing others to collaborate with you and collaborating well on projects initiated by others. <

NVIDIA's accelerated computing platforms move data at speeds that push the limits of what silicon and physics allow. Whether a high-speed interface trains reliably, maintains accurate margins, and survives every platform topology it will ever see is a question we answer ourselves. This role does that work. The Silicon Co-Design Group leads the boundary between what was designed and what was built. When a GPU, CPU, or SoC ships with interfaces that work at scale, this team is the reason. Most engineers debug within a layer. You will own the full stack. When an interface fails to train, the link margin is unexpectedly tight, or a customer reports a critical silicon issue, you trace the problem through protocol behavior, signal integrity, firmware, platform topology, and silicon marginalities. You then confirm that the fix works. Your methodology shapes how NVIDIA validates high-speed interfaces across generations. Your decisions affect yield, production ramp, and field quality. This is not a coordination role. The engineers who do it well hold protocol depth and system breadth simultaneously, never lose the thread across hardware, firmware, and software, and have the judgment to know when to go deeper and when to act. They are rare. Should that describe you, read on. What you'll be doing: Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness. Close the hardest failures. Drive root cause across protocol behavior, signal integrity, firmware and driver interactions, platform topology, and silicon marginalities and own every fix through to confirmation. Define validation strategy. Set test coverage, debug priorities, margining methodology, and stress criteria f

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Diffusion Process Development Engineer, you will act as a technical leader accountable for FEOL diffusion, annealing, and gate oxidation process advancement for advanced DRAM devices! This position emphasizes gate dielectric scaling, process reliability, and manufacturing preparedness. The ideal candidate blends extensive expertise in diffusion processes, oxidation principles, and device physics with practical experience transitioning technologies from development to production. You will collaborate closely with groups dedicated to process development, device engineering, equipment, and manufacturing to support future technology nodes. This role requires work with AI for productivity. Key Responsibilities Lead the progress of FEOL diffusion, thermal treatment, and gate oxidation operations in advanced DRAM technology. Develop and scale ultra-thin gate dielectrics, balancing electrical performance, reliability, variability, and manufacturability. Drive process development from concept through integration, pilot qualification, and manufacturing transfer. Evaluate, qualify, and optimize diffusion and oxidation equipment platforms and reactor builds. Define and monitor manufacturing metrics, including statistical process control, process capability, defectivity, and variability. Interpret electrical, physical, and materials characterization data to guide development decisions. Partner with external suppliers to develop hardware and processes aligned with future technology