HBM Advanced Package Process / Equipment Engineer

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities and Tasks: • Accountable and sustain for Bond process. • Backup for Debond area process basic maintenance. • Establish and improve process condition and technology. • Upgrade tool capability and improve product quality. • Establish and modify process management projects. • Set up process parameters for a variety of semiconductor equipment. • Evaluation, promotion and planning of new equipment / materials. • Abnormal analysis and improvement. • Leveraging AI and data analytics tools to enhance process monitoring, root cause analysis, predictive maintenance, and process optimization. Qualifications and Skills • Experience in wafer bonding, debonding, coating, lithography, thin film, or advanced packaging processes is preferred. ​ • Establish and improve process condition and technology.​ • Upgrade tool capability and improve product quality.​ • Establish and modify process management projects.​ • Set up process parameters for a variety of semiconductor equipment. ​• Evaluation, promotion and planning of new equipment / materials. ​• Abnormal analysis and improvement.​ • Leveraging AI and data analytics tools to enhance process monitoring, root cause analysis, predictive maintenance, and process optimization for semiconductor manufacturing operations. Requirement:​

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Intro: The Advanced Packaging Technology Development (APTD) department at Micron Technology is advancing next-generation packaging technologies that enable the performance and scalability requirements of tomorrow’s AI and high-performance computing applications. Our team brings together experts in process integration, materials engineering, and semiconductor development to solve complex technical challenges and turn new ideas into production-ready solutions. Join us and help shape the future of advanced memory and packaging technology! Position Overview: As a Process Integration Engineer for Advanced Packaging, you will play a key role in developing and integrating advanced package architectures, including 2.5D, 3D stacking, HBM, and hybrid bonding technologies. You will work across engineering disciplines to develop new processes, improve performance and yield, and support the transfer of emerging technologies into manufacturing. This is an opportunity to contribute to innovative products while working on some of the industry's most advanced packaging solutions. Responsibilities: Develop and optimize advanced packaging technologies, including 2.5D/3D integration, HBM, hybrid bonding, and advanced interconnects Design and execute experiments to qualify materials, process flows, and design rules for new package architectures Analyze yield, performance, and defect data to identify process improvements using SPC and advanced analytics Drive

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for the most advanced AI/HPC silicon and package design. This role focuses on high-speed SerDes and memory channel architecture, advanced 2.5D/3D package SI/PI, substrate to package co-design, power-delivery-network optimization, electromagnetic modeling, and simulation-to-measurement correlation. The ideal candidate has strong hands-on experience with high-speed channel and PDN analysis across ASIC packages, interposers, substrates, and power-delivery structures, and can translate simulation results into practical design requirements for interposers and package substrate design optimization. The engineer will work closely with ASIC, package, system, mechanical, thermal, power, and silicon validation teams from early architecture and feasibility studies through production bring-up. In this role you will Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility studies through production. Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces. Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers. Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps based on SI/PI re

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The HBM Design Technology Package Co-Optimization (DTPCO) organization is seeking a Staff Engineer! Lead the design and development of test vehicles that enable technology learning and risk reduction for future HBM products! This role serves as a key technical contributor within DTPCO, partnering closely with Architecture, Design, Layout, Product Engineering, Reliability, and Advanced Packaging teams to translate emerging product requirements and technology challenges into actionable test vehicle solutions. You will apply expertise in semiconductor design, physical implementation, silicon characterization, and advanced packaging technologies to define test structures, develop validation strategies, and generate data that drives product decisions across future HBM generations. Unlike a traditional product role centered on ownership of product blocks, this position emphasizes enabling learning in development and engineering. It does so by developing representative test vehicles and characterization structures. Key Responsibilities Serve as a technical lead for HBM test vehicle design and structure development within DTPCO. Partner with HBM product, technology and reliability team. Define and implement test structures targeting key learning areas such as package interaction and reliability Drive test vehicle content definition, structure specifications, measurement requirements, and validation objectives. Analyze silicon characterization and qualification results to identify optimization opportunit

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Intro: We are advancing the future of semiconductor packaging through innovative 2.5D, 3D, and heterogeneous integration technologies. Our team develops the processes that enable next-generation AI and high-performance computing products, working across materials, device, design, manufacturing, and test engineering to solve complex technical challenges. If you're excited by emerging packaging architectures and breakthrough integration approaches, you'll find meaningful opportunities to make an impact here. Position Overview: As a Process Integration Lead for Advanced Packaging, you will lead a team focused on developing and integrating advanced packaging technologies from concept through full-scale manufacturing. This role plays a critical part in enabling high-performance multi-die solutions by driving technology development, process integration, technology transfer, and collaborative execution. You will help shape the roadmap for next-generation packaging platforms while mentoring a highly skilled technical team. Responsibilities: Manage and grow a team responsible for seamless process integration across 2.5D and 3D packaging platforms, including advanced interconnect architectures, die-stacking solutions, and HBM implementation. Spearhead the development, optimization, and qualification of emerging packaging technologies through experimental design (DOE), process analysis, performance validation, and establishment of design rules. Improve

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron Technology, we transform how the world uses information to enrich life for all. The Heterogeneous Integration Group (HIG) HBM Architecture team develops next-generation High-Bandwidth Memory (HBM) solutions that power AI, high-performance computing, cloud infrastructure, and advanced networking systems. The team works across architecture, design, verification, packaging, product engineering, and technology development to evaluate innovative memory architectures and deliver scalable, high-performance semiconductor solutions. As an HBM Design Architect, New College Graduate, you will contribute to the evaluation and development of future HBM and DRAM architectures. Working with experienced architects and engineering teams, you will analyze system and block-level design tradeoffs related to performance, power, area, thermal behavior, reliability, and manufacturability. This role provides an opportunity to leverage AI, Large Language Models (LLMs), and data-driven engineering methodologies to accelerate architecture exploration and improve decision-making. Responsibilities Analyze HBM and DRAM architectures using analytic