HBM ASSEMBLY PRODUCTION SUPERVISIOR

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. • Leverage AI-enabled and AI-assisted work methods, including Microsoft Copilot, Generative AI, and advanced analytics tools, to improve equipment utilization, yield performance, alarm code analysis, parts lifetime prediction, and manufacturing efficiency . • Utilize AI-powered data analysis to identify equipment performance gaps, predict equipment failures, optimize preventive maintenance strategies, and reduce unplanned downtime. • Apply AI-assisted troubleshooting techniques to accelerate root cause analysis of equipment alarms, process excursions, and yield loss mechanisms. • Familiar with TCB/DB process and possesses a minimum of 5 years of semiconductor equipment engineering experience . • Identify, diagnose, and resolve assembly equipment related issues utilizing data-driven and AI-supported methodologies. • Coordi nate and execute process, equipment, and material evaluations, leveraging AI insights to optimize manufacturing performance and quality. • Lead and participate in utilization improvement, yield enhancement, cost reduction, and smart manufacturing initiatives through automation and AI technologies. • Validate and qualify new processes

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Responsibilities Yield Loss Accounted For Account for HBM NPI builds across PWF, Assembly, and test through defect breakdown and PFA submission to understand fail mode Work closely with PI to identify defect that is coming from their area to brainstorm for CIP Learn NPI processes, phase gates, and yield best practices Assist in maintaining yield dashboards and trackers. Support PI/PE/RDA in identifying and transforming processing data to account/ breakdown a yield loss Yield Deviation Control Analyze and report on yield deviation issue and trigger action from PI, PE or RDA Support block run and partial conversion build yield analysis to early detect any impact on yield Work closely with PCS team to identify SPC or FDC charts to put into YLR dashboard for shift left monitoring Yield Improvement Opportunities Brainstorm with staff from other departments to brainstorm for improvement opportunities to propose to PI Utilize software tool like Auto-diagnostics to find yield improvement opportunities Integrating Artificial Intelligence Integrates AI-assisted tools and insights into daily work to improve efficiency, quality, or effectiveness, exercising sound judgement and complying with organizational standards and legal requirements Contributes to a culture of continuous improvement by identifying, testing, and sha

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Staff Design Engineer is responsible for designing, simulating, and optimizing DRAM circuits while supporting the development of digital and analog circuitry used in advanced memory products. This role collaborates globally across design, verification, product engineering, test, probe, process integration, assembly, and marketing to ensure manufacturable, high‑quality, cost‑optimized solutions. The position drives innovation in future memory generations and contributes to silicon‑to‑system development in a dynamic engineering environment. Responsibilities Design digital, analog, and memory core circuits using CMOS logic and transistors, implementing device specifications from concept to solution. Utilize AI-Enabled tools to assist with schematic editing, data collection and layout floorplan. Create optimized floorplans for circuit placement, routing, power delivery, sense margins, array timing, and die size, including layout leadership. Conduct circuit simulations using FINESIM, HSPICE, and VERILOG; analyze power, performance, reliability, and parasitic impacts. Validate builds through reticle experiments, tape‑out revisions, and simulation‑to‑silicon correlation, identifying required schematic edits. Prepare and maintain design documentation while contributing to best‑known practices and departmental training. Collaborate with global build, verification, product engineering, test, probe, process integration, assembly, and marketing teams to ensure manufacturability and quality. <l

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about driving innovation for next-generation memory solutions powering AI/ML and high-performance computing systems. As a Director of HBM RTL Design and Integration, you will lead a team responsible for the design, integration, and delivery of next-generation HBM SoC logic die, with a strong focus on RTL development and IP integration. You will drive technical strategy and execution across multiple product generations, working closely with architecture, verification, physical design, firmware, and product engineering teams. Key Responsibilities Lead SoC RTL design and integration for HBM logic die, including subsystem partitioning, IP integration, and SoC-level design convergence. Drive translation of architectural and micro-architectural specifications into robust, high-quality RTL implementations across multiple teams. Oversee SoC integration aspects, including clocking, reset, power intent, configuration infrastructure, and system-level design correctness. Establish design methodologies and best practices to improve quality, reuse, and development efficiency across HBM programs. Partner with SoC Architecture, Verification, Physical Design, Firmware, and System teams to ensure successful end-to-end product execution. Work closely with Product Engineering, Test, Probe, Process Integration, Assembly, and Manufacturing to ensure robust, manufacturable HBM

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Sr Design Engineer, you will work on design, simulation, and validation of next ‑ generation High ‑ Bandwidth Memory (HBM) architectures and circuit blocks. HBM requires advanced DRAM design knowledge combined with deep understanding of 3D stacked architecture, TSV signaling, wide I/O interfaces, PHY timing, power integrity, and system co ‑ optimization with GPUs/accelerators. This role sits at the intersection of DRAM design and high ‑ performance computing, enabling future AI/ML, HPC, and advanced graphics products. In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a HIG IE Engineer, your responsibilities encompass tactical execution and planning to support tactical pillar, CAPEX and OCAP budget management, material planning for wafer probe C1-C4 to Micron IQP, build Business Processes to enable wafer level activities. Also to work as a window for wafer PRIME, pWLR and DOE material acquisition, drive sample deliveries to execution for Wafer Reliability and IQP Reliability. You are also expected to understand procurement of items, inventory logistic management, audits, continual improvements, 6S housekeeping, and project management. It is a must for a HIG PSE IE Engineer to be familiar with Claude Code, AI apps and leveraging AI for work productivity and quality improvements. Responsibilities include, but are not limited to: Able to utilize Claude Code and AI apps in regular work. Proven creation of Claude Code apps (Advantageous with more than one creation) Have clear knowledge of HBM wafer probe operations starting from Assembly to post C4. Have clear knowledge of wafer material acquisition from FE processes. Liaison with NPO, SIC, NPI teams from F15 and OMT. Have knowledge in MES/MAM attributes, tagging of lots from AAA, DAA and NAA lots. Familiar with CBG setting to ensure engineering wafers are not mixed with MFG wafers. Able to track E2E DOEs requests from start to CRD/MAD. Work closely with requestors on process needs. Able to work as a team with fellow members in a safe, cohesive, and collabo