About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for the most advanced AI/HPC silicon and package design. This role focuses on high-speed SerDes and memory channel architecture, advanced 2.5D/3D package SI/PI, substrate to package co-design, power-delivery-network optimization, electromagnetic modeling, and simulation-to-measurement correlation. The ideal candidate has strong hands-on experience with high-speed channel and PDN analysis across ASIC packages, interposers, substrates, and power-delivery structures, and can translate simulation results into practical design requirements for interposers and package substrate design optimization. The engineer will work closely with ASIC, package, system, mechanical, thermal, power, and silicon validation teams from early architecture and feasibility studies through production bring-up. In this role you will Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility studies through production. Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces. Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers. Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps based on SI/PI re
Employment
FULL TIME
Work mode
On-site
Experience
SENIOR LEVEL
Salary
Not disclosed
Salary not disclosed
Check market pay for comparable HBM SIPI roles before applying.
Role overview
Job description
HBM SIPI, Staff Engineer — 2 Locations. Apply via Workday.
Hiring company
Micron Technology
Explore this employer's active roles, salary signals and company profile on Jobiba.
Keep exploring
Similar active roles
Fresh roles matched to this title and market.
NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems Engineer at NVIDIA, you'll join a group of hardworking engineers to develop and architect innovative Memory Solution for Tegra SoCs. In this position, you'll make a real impact in a multifaceted, technology-focused company. You will work with memory controller/PHY and Platform / System architect, Firmware, SI/PI, Memory suppliers to design and architect cutting edge, high speed and lower power memory technology for NVIDIA CPUs and SOCs. What You Will Be Doing: Analyze future DDR/LPDDR/HBM technologies to determine optimum performance, power, function and RAS in memory for Next generation SOC and Systems. Collaborate with ASIC Architects, Designers, Software and Firmware SW/FW teams to drive memory technology and associated requirements for memory controllers. Define Memory module, Package, and PCB layouts appropriate to the system workloads Debug and bring up memory evaluation / validation and failure issues on memory technology. Collaborate with DRAM suppliers and industry partners on to develop memory and memory related component technology. What We need to see: Bachelor's degree or master’s degree in Electrical Engineering, Computer Engineering (CE), or a related field (or equivalent experience) 10 years of proven track record in DRAM design, module design, or memory sub system design. Deep understanding and strong fundamental of memory design, features, ECC algorithm, SI and PI (Training algorithm) in DDR, LPDDR, and HBM. Strong understanding of memory sub system level interaction with Cache, Memory controller and PHY. Experience in the design, bring-up and validation for memory failure analysis Experience with Python, C/C
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet ambitious power, performance, area, and schedule targets. You will also work to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic). Collaborate with SoC architects to translate architectural and micro‑architectural specifications into high‑quality RTL implementations. Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure. Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues. Contribute to design documentation, block specifications, and design reviews. Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds. Minimum Qualifications Bachelor’s or master’s degree in electrical engineering, Computer Engin
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities and Tasks: • Accountable and sustain for Bond process. • Backup for Debond area process basic maintenance. • Establish and improve process condition and technology. • Upgrade tool capability and improve product quality. • Establish and modify process management projects. • Set up process parameters for a variety of semiconductor equipment. • Evaluation, promotion and planning of new equipment / materials. • Abnormal analysis and improvement. • Leveraging AI and data analytics tools to enhance process monitoring, root cause analysis, predictive maintenance, and process optimization. Qualifications and Skills • Experience in wafer bonding, debonding, coating, lithography, thin film, or advanced packaging processes is preferred. • Establish and improve process condition and technology. • Upgrade tool capability and improve product quality. • Establish and modify process management projects. • Set up process parameters for a variety of semiconductor equipment. • Evaluation, promotion and planning of new equipment / materials. • Abnormal analysis and improvement. • Leveraging AI and data analytics tools to enhance process monitoring, root cause analysis, predictive maintenance, and process optimization for semiconductor manufacturing operations. Requirement:
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities and Tasks Your main task will be operating Equipment. Manning of multiple machines Demonstrate ability to use computer based programs and applications to perform daily duties Provide machine coverage during breaks Logging machines accurately Monitoring and awareness of equipment performance discrepancies with timely communication to your Lead Working hours are fixed night shift , 19:30 to 07:30, following a 4-3 rotation schedule (four days on, three days off; three days on, four days off). Ensure Quality of Process and Product Run equipment based on current process specifications (e.g. procedures, change notifications, etc.) Organize own workstations and ensuring 6S Make suggestions to improve quality and safety Complete Certification and Recertification Participate actively in assigned on-the-job and other required training; asking questions to increase knowledge and abilities Complete certification requirements by demonstrating understanding and abilities Communication Information Receive and understand pass down, providing clear, accurate, and detailed pass down Seek and provide feedback to leadership, coworker, and support groups to make positive changes in performance Offer suggestions towards improvements when appropriate Always seek clarification when in doubt Contribute to a Safe and Compliant Work Envi
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Responsibilities Yield Loss Accounted For Account for HBM NPI builds across PWF, Assembly, and test through defect breakdown and PFA submission to understand fail mode Work closely with PI to identify defect that is coming from their area to brainstorm for CIP Learn NPI processes, phase gates, and yield best practices Assist in maintaining yield dashboards and trackers. Support PI/PE/RDA in identifying and transforming processing data to account/ breakdown a yield loss Yield Deviation Control Analyze and report on yield deviation issue and trigger action from PI, PE or RDA Support block run and partial conversion build yield analysis to early detect any impact on yield Work closely with PCS team to identify SPC or FDC charts to put into YLR dashboard for shift left monitoring Yield Improvement Opportunities Brainstorm with staff from other departments to brainstorm for improvement opportunities to propose to PI Utilize software tool like Auto-diagnostics to find yield improvement opportunities Integrating Artificial Intelligence Integrates AI-assisted tools and insights into daily work to improve efficiency, quality, or effectiveness, exercising sound judgement and complying with organizational standards and legal requirements Contributes to a culture of continuous improvement by identifying, testing, and sha
🔔 Get job alerts
New HBM SIPI, Staff Engineer jobs in 2 Locations, straight to your inbox.
No spam · Unsubscribe anytime