Link Validation Engineer

Job Details: Job Description: Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below. Life at Intel The Role and Impact As a SoC Power Thermal Performance Validation and Optimization Engineer, you will play an essential role in ensuring Intel's products achieve optimal power, thermal, and performance benchmarks at the system-on-chip (SoC) level. In this position, you will develop and execute validation methodologies, optimize hardware/software solutions, and perform SoC-level debugging to address power, thermal, and performance challenges. Your contribution will directly impact Intel's ability to deliver competitive, high-performing products to market. Business Group This role is part of Intel's Data Center Group (DCG), which focuses on designing innovative solutions to power the next generation of computing platforms for data centers. As a member of the PTP PreSi Correlation Solution team, you will contribute to shaping the development and validation processes for cutting-edge technologies, ensuring Intel meets and exceeds industry standards for performance and efficiency. Key Responsibilities: Develop and execute SoC-level power, thermal, and performance validation and

About the job Debug the high-speed interfaces that decide whether advanced AI systems perform in the real world. As a Validation and Debug Engineer, you will help prove Graphcore silicon and platforms work across real product conditions. You will build deep knowledge of our devices, boards and system behaviour. You will own hands-on validation and debug in the lab, focused on SerDes, PCIe Root Complex and Ethernet. Your work will help resolve complex issues across silicon, hardware, firmware and architecture teams. This role is for someone who enjoys getting close to the hardware. You will tune links, investigate failures and turn difficult lab findings into clear engineering decisions. The team and culture You will work closely with Architecture, Silicon Engineering, Hardware Engineering and Firmware. Progress comes through practical evidence, clear communication and fast problem solving. The team expects ownership without daily oversight. You will drive bring-up, debug issues and help teams reach decisions based on data. You will be trusted to speak up when something is unclear or risky. The best ideas can come from anyone close to the problem. What we’re looking for · Strong hands-on hardware validation experience, including board bring-up and subsystem debug · Experience validating and debugging Ethernet, PCIe Root Complex and SerDes systems · Confident use of lab instrumentation, including oscilloscopes, BERT systems, VNA/TDR equipment and PCIe protocol analysers · Ability to debug signal integrity, protocol-level and interface issues through to root cause · Experience with PCIe bring-up, LTSSM analysis, link training, equalization tuning and interoperability testing · Ability to work independently, take responsibility and drive issue resolution across teams While we have outlined a set of requirements, we value transferable skills and diverse experiences. If you meet most of our essential criteria, we encourage you to submit an application and showcase how you

NVIDIA is looking to hire a Test Engineer in Roskilde, Denmark for the development of silicon photonics and semiconductor devices that will link-up the datacenters of tomorrow. The successful candidate will work on electrical and optical device test program development, including technical management of development projects with multiple partners from across the organization. This role is an opportunity to work on NVIDIA core technology under development. What you'll be doing: Develop and implement electrical semiconductor test programs, collaborating closely with international teams to build solutions that ensure flawless execution. Perform device characterization and conduct data analysis to provide quality feedback to designers. Partner with internal teams to ramp new silicon from development to product and hand over to production teams. Improve yield and reduce test time through innovative solutions. What we need to see: A B.Sc/M.Sc in Electrical Engineering or Physics from a reputable university, or equivalent experience. Demonstrated experience in electrical engineering and programming. Over 2 years of experience in the semiconductor industry. Experience in photonic or semiconductor testing or validation, along with programming languages like Python and VBA. New outstanding graduates will also be considered. Ways to stand out from the crowd: Strong knowledge of probability and statistics tools, such as JMP. A new way of problem-solving that drives success. Experience leading cross-organizational activities with a high sense of responsibility. Join us in our mission to pioneer the next generation of computing and leave a lasting mark on the world. At NVIDIA, you will be part of a

NVIDIA's accelerated computing platforms move data at speeds that push the limits of what silicon and physics allow. Whether a high-speed interface trains reliably, maintains accurate margins, and survives every platform topology it will ever see is a question we answer ourselves. This role does that work. The Silicon Co-Design Group leads the boundary between what was designed and what was built. When a GPU, CPU, or SoC ships with interfaces that work at scale, this team is the reason. Most engineers debug within a layer. You will own the full stack. When an interface fails to train, the link margin is unexpectedly tight, or a customer reports a critical silicon issue, you trace the problem through protocol behavior, signal integrity, firmware, platform topology, and silicon marginalities. You then confirm that the fix works. Your methodology shapes how NVIDIA validates high-speed interfaces across generations. Your decisions affect yield, production ramp, and field quality. This is not a coordination role. The engineers who do it well hold protocol depth and system breadth simultaneously, never lose the thread across hardware, firmware, and software, and have the judgment to know when to go deeper and when to act. They are rare. Should that describe you, read on. What you'll be doing: Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness. Close the hardest failures. Drive root cause across protocol behavior, signal integrity, firmware and driver interactions, platform topology, and silicon marginalities and own every fix through to confirmation. Define validation strategy. Set test coverage, debug priorities, margining methodology, and stress criteria f

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 47 years, Micron Technology, Inc. has driven innovation through advanced memory and semiconductor technologies that power the world's computing platforms. The DRAM Customer Enablement team serves as a critical link between Micron's newest memory solutions and the systems that deploy them across cloud, AI, enterprise, client, mobile, and next-generation computing environments. The group committed to DRAM Customer Enablement works closely with hardware, firmware, systems, validation, and analytics engineers to ensure successful deployment of new DRAM technologies. Through system validation, reliability analysis, automation, and customer enablement activities, the team helps bring Micron's latest innovations to market. As an intern, you will gain hands-on experience working with sophisticated memory technologies, modern server and computing platforms, and AI-assisted software development tools. You will contribute to real engineering projects involving platform bring-up, validation, interpreting data, developing automated solutions, and technical problem solving while collaborating with experienced engineers across multiple fields. Responsibilities Support bring-up, validation, characterization, and debugging of server, client, and mobile platforms using Micron DRAM technologies. Analyze engineering and customer data to identify performance trends, reliability concerns, and system-level insights; create dashboards, visualizations, and technical reports to communicate findi

Who We Are HP IQ is HP’s new AI innovation lab. Combining startup agility with HP’s global scale, we’re building intelligent technologies that redefine how the world works, creates, and collaborates. We’re assembling a diverse, world-class team—engineers, designers, researchers, and product minds—focused on creating an intelligent ecosystem across HP’s portfolio. Together, we’re developing intuitive, adaptive solutions that spark creativity, boost productivity, and make collaboration seamless. We create breakthrough solutions that make complex tasks feel effortless, teamwork more natural, and ideas more impactful—always with a human-centric mindset. By embedding AI advancements into every HP product and service, we’re expanding what’s possible for individuals, organisations, and the future of work. Join us as we reinvent work, so people everywhere can do their best work. About The Role HP IQ's Wireless Technology Team works cross-functionally with Electrical Engineering, Software, Mechanical Engineering, Product Design, Industrial Design, Program Management, and Operations to develop next-generation wearable and AI-connected products. As a Lead RF Systems & Desense Engineer, you will own the RF system architecture from concept through mass production. You will lead RF integration across Wi-Fi, Bluetooth, UWB, NFC and emerging wireless technologies while driving RF desense, coexistence, and wireless performance for highly integrated products. What You Might Do Lead RF system architecture and integration for wearable and mobile platforms. Own RF desense investigations and mitigation across the product lifecycle. Define RF specifications, link budgets, validation plans and performance targets. Lead coexistence strategy for Wi-Fi, Bluetooth, UWB, NFC and other radios. Partner with antenna, EE, FW, ME and silicon vendors to optimize total wireless performance. Perform CST and ADS simula