Mixed Signal IC Layout Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a highly skilled Physical Design Engineer to drive the critical Die-to-Die (D2D) Physical Implementation from RTL to GDSII. This role demands deep expertise in full physical design flow with a specific focus on closing high-speed D2D interfaces for multi-die/chiplet architectures. This role is remote role open to any location in the U.S. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned ASIC Physical Design Engineer with 5+ years at advanced nodes (7nm or below) and multiple successful tapeouts. Strong in full-chip implementation, comfortable owning blocks from RTL to GDSII across synthesis, floorplanning, place-and-route, CTS, and sign-off. Deeply familiar with high-speed interfaces (D2D, PCIe, HBM, SerDes) and the physical challenges that come with them (timing, signal integrity, power integrity). Detail-oriented and methodical with STA, constraints, and closure for complex, high-speed designs. A hands-on problem solver who enjoys collaborating across analog, digital, and full-chip teams to debug tough issues. What We Need Lead Die-to-Die (D2D) physical implementation and closure, taking high-spe

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Overview The Non-Volatile Engineering Group (NVEG) at Micron develops memory products that are best-in-class in die size, performance, reliability, and power! Our mission is to innovate and deliver groundbreaking non-volatile memory solutions such as NAND. As the pace of technology accelerates, NVEG is aggressively embedding AI across every stage of the design flow — from circuit exploration and layout optimization to silicon debug and specification analysis — and we are looking for engineers who not only use AI in their daily work but also actively reshape our engineering workflows to unlock AI’s full potential! Position Overview As a Principal Design Engineer in NVEG, you will architect, design and sign off the high-speed IO interface of next-generation NAND flash, moving data between the NAND die and the host controller at multi-GT/s rates under tight power, area and signal-integrity limits. You will own IO blocks end to end, from spec and architecture through circuit design, layout guidance, verification and silicon correlation. You will set IO architecture direction across products, lead task forces, and make the key trade-offs that hit aggressive data-rate and power targets. AI is a central pillar of how this team works: you will use AI tools daily and reshape wor

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Design and implement physical layouts for advanced digital, analog, and mixed-signal circuits used in the development of memory products. Responsible for translating schematics into high quality, manufacturable layouts that meet process rules, performance targets, and schedule commitments, while collaborating closely with cross functional engineering teams. Create physical layouts of transistors, resistors, capacitors, and interconnect structures for digital, analog, and mixed-signal circuits. Perform block-level floor planning, including layout area estimation and optimization. Develop IC top-level floorplans and provide accurate total die area estimates. Execute routing, power bus design, and creation of robust PDN (Power Domain Network) solutions to ensure optimal electrical performance, reliability, and scalability. Ensure layouts comply with foundry process design rules and verify layout-versus-schematic (LVS) and design rule checks (DRC). Apply recommended layout, verification techniques, tools, and design flows to deliver high-quality designs on schedule. Work closely with analog/mixed-signal and digital design engineers to ensure proper layout implementation, including critical matching and symmetry requirements. Collaborate with Design Engineering, Product Engineering, Process Integration, Probe, and Assembly teams to proactively optimize designs for manufacturability, cost, quality, reliability, and time-to-market. Create and maintain layout-related documentation and actively participate in layout and design reviews. Support continuous improvement of

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s Design Engineering Group (DEG) is where bold ideas become real technology. We push the limits of memory and storage innovation, and we thrive in a collaborative environment where engineers learn, build, and solve challenges together. We are driven by curiosity, creativity, and the pursuit of better solutions every day! As a Design Engineer, you will help shape the next generation of Micron’s memory products. You’ll work closely with global design, verification, and product teams to bring innovative circuit designs from concept to silicon. Your work will directly influence product performance, quality, and reliability—and contribute to advancements that define the semiconductor industry. Responsibilities: Design, optimize, and verify block‑level circuits for DRAM projects Compare silicon performance with simulation results and support correlation activities Collaborate with process integration and modeling teams on new process node development Partner with global design groups and provide layout guidance through post‑layout simulation Minimum Qualifications: Bachelor’s degree in Electrical Engineering with 2+ years of semiconductor design or manufacturing experience Demonstrated experience in mixed-signal, digital, or analog IC design Experience designing regulators, charge pumps, oscillators, current references, bandgaps, or comparators Proficiency with SPICE and Verilog modeling and simulation Experience working wi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description: As a Mixed-Signal Design Engineer in Micron’s Pathfinding Design Team, you will play a key role in crafting next-generation memory technologies. This position involves contributing to defining, developing, and analyzing high-speed logics to operate the memory. These paths span from the memory array to the interface block for memory technologies, including DRAM and emerging memories. You will work on novel concept development, circuit simulation, optimization, and floor planning to enable groundbreaking memory solutions! Responsibilities: Provide technical direction and design implementation for a memory control circuits (both of digital and analog) from the memory array to the interface block. Collaborate closely with physical design teams to ensure timing closure, CDC robustness, and power intent alignment. Demonstrated experience working with custom mixed-signal IC build and development for volatile or nonvolatile memory technology. Experience with modeling and simulation of ICs using HSPICE/finesim. Minimum Qualifications: Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related field. 7&#43; years of experience in custom mixed-signal circuit design. Proficiency with UNIX and CADENCE design environment (Simulation, Schematic entry, SPF extraction) </

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s Interface Pathfinding team builds and validates innovative PHY solutions for high-speed chip-to-chip and memory interconnect. Our focus is on pushing the boundaries of what is possible in high-speed signaling and validating those boundaries with real hardware data. As a Principal Analog Design Engineer, you will be at the forefront of developing custom and original analog circuits. This is not integration or maintenance work, but an ambitious opportunity to contribute to world-class clocking, transmitter, and receiver circuits. You will own the complete lifecycle of building, from specifications through to post-silicon characterization. Responsibilities: Lead the development of specialized analog components, focusing primarily on clocking (PLL, DLL, CDR) and transmitter/receiver circuits. Contribute to the top-level PHY analog architecture decisions, including clocking topology and signal chain partitioning. Build and maintain transistor-level simulation testbenches; perform process corner, statistical sampling, and evaluate variations to characterize build margin and yield sensitivity. Define and detail clear interface specifications between custom analog blocks and the digital control wrapper. Collaborate closely with the layout team to guide custom analog layout and support post-silicon characterization in the lab. Minimum