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Active4w ago

Packaging Engineer- Bump Interconnect

Volantis Semiconductor, Inc.·📍 Hybrid Remote/Sf Bay Area/Austin/Boston

Employment

Full-Time

Work mode

Hybrid

Experience

All levels

Salary

Not disclosed

Salary not disclosed

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Role overview

Job description

We’re seeking an experienced engineer to lead bump interconnect development for advanced semiconductor devices (2.5D/3D/chiplet/fan-out). This role spans ubump and C4 bump metallurgy, RDL design and plating, chip-side and interposer capture pad design rules, OSAT engagement, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities Own end-to-end bump interconnect development for both ubump (micro-bump) and C4 processes, including bump formation, and reflow for use with mass reflow, TCB, and LAB chip attach for high-performance semiconductor packages. Define and own bump metallurgy stacks for ubump (e.g., Cu pillar/SnAg) and C4 (e.g., SAC alloys) interconnects, including UBM selection and pad finish specifications for both chip-side and interposer capture pads. Develop and own design rules for bump interconnects inc

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What they are looking for

Skills & requirements

Qualification

Support reliability qualification including thermal cycling, drop, mechanical shock, and power cycling

Department · Advanced Packaging

VS

Hiring company

Volantis Semiconductor, Inc.

Technology

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