Senior CPU Front End Methodology Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer who will contribute to the physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout. You will partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs. Along the way, you will build end-to-end ASIC expertise while learning from experienced engineers across the chip development process. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An engineer excited to work on high-performance designs for industry-leading AI/ML architectures. A collaborative problem solver who enjoys working with experienced engineers across ASIC disciplines. Grounded in logic design fundamentals and gate- and transistor-level implementation. Curious about how early architectural and RTL decisions shape physical implementation and final chip quality. What We Need A BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a relat

Job Details: Job Description: As a Senior Power and Performance (PnP) Engineer, you will be responsible for PnP product execution focused on measurements, analysis, and projections/estimates of Intel's unlaunched notebook and desktop products. Based on your technical knowledge of both Intel and the competition, you will help influence OEM customers, internal marketing teams, internal engineering teams, debug Intel silicon/platform on PnP issues, and be an integral part for Intel product launches. Core responsibilities to include following: Measure, analyze, and debug workloads to call out any power and/or performance gaps and close with internal engineering teams/architects Measure and analyze SoC/CPU and platform power on a rail by rail basis and debug any issues/gaps Align with other internal engineering teams and architects to ensure there is consensus on power and performance projections/estimates/measurements for both internal and external communication Guide, educate, and influence internal engineering teams, field account teams, and marketing teams on power and performance positioning of Intel products Create power and performance estimates on upcoming Intel products based on workloads to aid marketing decisions and help set internal KPI targets Own the publication of the Power Performance Guide (PPG) collateral to help guide OEM customers Bring up full test platform to enable both power and performance measurements including setup, calibration, and measurements. Qualifications: You mus

Job Details: Job Description: Do Something Wonderful At Intel, we put silicon at the center of the world’s most meaningful innovations. From personal computing and AI to cloud-scale data centers and edge platforms, our processors power technologies that touch billions of lives. If you’re passionate about building world-class silicon at massive scale, we want to build the future with you. The Team You’ll join Intel’s All Cores Engineering (ACE) organization, the team responsible for designing and delivering Intel’s industry‑leading CPU cores. Within ACE, the Atom group focuses on high‑efficiency, performance‑per‑watt optimized cores that enable everything from client platforms to emerging edge and scalable solutions. This is a hands‑on senior engineering role with direct impact on next‑generation CPU silicon. What You’ll Do As a Senior CPU Design Verification Engineer you will play a critical role in ensuring architectural correctness, functional robustness, and power‑efficient performance of Intel’s Atom CPU designs before first silicon. Key responsibilities include but not limited to the following: Lead pre‑silicon functional verification of complex CPU and SoC logic to ensure full compliance with architectural and microarchitectural specifications. Develop and execute verification plans, testbenches, and SystemVerilog/UVM environments, ensuring comprehensive functional and coverage closure. Define, run, and analyze system‑level simulations to uncover functional, performance, power, and corner‑case issues. Debug and root‑cause complex RTL, microarchitecture, and integration issues; drive issues to resolution with design teams. Collaborate cross‑functionally with CPU architects, RTL de

Join our multidisciplinary team and help build and improve GPU and CPU accelerated data processing software libraries. Projects like DALI or nvImageCodec are used in all kinds of processing workflows and support NVIDIA's vision and growth. Starting from powering AI, data analytics, image processing, computer vision, and scientific simulations for leading commercial and academic organizations worldwide. In this role, you will design, develop, and optimize pioneering algorithms. Ideal candidates will have experience with accelerated computing and a passion for advancing the state-of-the-art in various computing domains. If this sounds exciting, we would love to meet you! What you’ll be doing: Developing scalable library software using modern tools and languages for various numerical method. Performance tuning, optimization, and benchmarking of algorithms on various architectures. Working closely with leadership team and other internal and external partners to understand feature and performance requirements and contribute to the technical roadmaps of libraries. Providing technical leadership and guidance to library engineers working with you. Find opportunities to improve user experience and library performance. What we need to see: PhD or MSc’s degree in Computational Science, Computer Science, Applied Math, or related science or engineering field of study is preferred (or equivalent experience). 5+ years experience developing, debugging, and optimizing high-performance parallel numerical applications on modern computing platforms, with GPU acceleration using CUDA. C/C++ programming and software development skills. Proven experience in leading and completing software development projects. Strong collaboration, communicati

... Address: 14 2 Samarth Nagar Ramtekdi Industrial Area Hadapsar Pune Maharashtra 411013. Facility: CPU PUNE Qualification: 10th Experience: 6 - 7 years Source: Sodexo India | Job Code: IJP566937

... Address: 14 2 Samarth Nagar Ramtekdi Industrial Area Hadapsar Pune Maharashtra 411013. Facility: CPU PUNE Qualification: Diploma Experience: 6 - 7 years Source: Sodexo India | Job Code: IJP566809