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Active1mo ago

Senior RTL Engineer, Interconnect Design

OpenAI·📍 San Francisco, California, United States

Employment

FULL TIME

Work mode

On-site

Experience

SENIOR LEVEL

Salary

Not disclosed

Salary not disclosed

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Role overview

Job description

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to en

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What they are looking for

Skills & requirements

Department · Scaling

O

Hiring company

OpenAI

Technology

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