Silicon Engineer

About the Role We’re seeking an Associate General Counsel to lead commercial legal strategy and execution for OpenAI’s silicon initiatives and the semiconductor ecosystem that supports our AI infrastructure. This is a senior, highly cross-functional role for a lawyer who can advise business and technical leaders across the semiconductor development, manufacturing, and supply lifecycle. The role will partner closely with silicon engineering, infrastructure, strategic sourcing, supply chain, manufacturing, finance, partnerships, IP, policy, regulatory, and trade compliance teams to structure and negotiate strategic arrangements with semiconductor ecosystem partners, technology providers, and critical suppliers. This person will help establish the commercial frameworks needed to protect OpenAI’s technology and support resilient, scalable commercial arrangements. We’re looking for an experienced technology transactions lawyer with meaningful semiconductor industry experience who can translate highly technical and operational issues into practical commercial structures. The ideal candidate combines strong judgment, commercial creativity, and the ability to lead complex, high-value transactions in a fast-moving and complex global ecosystem. This role is based in San Francisco, CA. We use a hybrid work model of 3-days in the office per week and offer relocation assistance to new employees. This role will: Lead commercial legal strategy and risk management for OpenAI’s silicon and related technology initiatives. Advise senior business, engineering, sourcing, and operational stakeholders on strategic relationships, commercial priorities, and complex transactions. Draft, negotiate, and advise on sophisticated development, manufacturing, supply, licensing, services, and strategic partnership agreements. Structure commercial arrangements that support long-term business and operational requirements. Advise on the commercial and operational issues that arise across the developmen

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for a software engineer to help build the design methodology, software abstractions, and infrastructure that enable a small silicon team to develop complex chips rapidly and with high confidence. You will turn evolving architecture and design needs into reusable tools and workflows that improve iteration speed, quality, and then apply those tools to help construct world-class silicon. You’ll work closely across architecture, design, verification, performance modeling, and systems software. This role is well suited for an engineer who enjoys building high quality software and is motivated by the challenge of improving velocity and quality of the silicon development process. In this role, you will: Develop and scale design methodologies for rapid first-party chip development and apply them to construct complex custom chips Create abstractions that allow hardware structures, configurations, experiments, and results to be represented consistently across tools. Automate high-value engineering workflows and improve their reproducibility, observability, testability, and ease of use. Partner with architects, RTL designers, verification engineers, compiler engineers, and systems software engineers to gather requirements and then implement solutions. Use methodology and tooling to identify design risks early, accelerate iteration, and improve confidence in performance and implementation tradeoffs. Contribute across multiple aspects of software and hardware

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will work on the systems software strategy and execution that brings new AI silicon from first power-on to a fully integrated system running production-representative models at expected functionality and performance. You will define how software exercises and validates compute, memory, interconnect, and I/O subsystems, then build the diagnostics, automation, and observability needed to find issues quickly. This role sits at the center of silicon, firmware, platform, systems, and workload teams. You will turn hardware specifications and performance targets into an end-to-end bringup plan, drive cross-functional debug, and establish the stress and regression infrastructure that makes each new platform reliable across operating environments. In this role, you will: Contribute to the end-to-end software bringup and validation strategy for new silicon and first-party systems. Define software-driven test coverage across compute, memory, interconnect, I/O, and their system-level interactions. Build diagnostics, test automation, telemetry, and regression infrastructure that accelerate first-silicon learning and issue isolation. Lead bringup from initial silicon arrival through board and system integration, docking, runtime enablement, and model execution. Design stress tests that characterize reliability, performance, and stability across workloads and operating conditions. Translate architecture specifications and performance models into measurable acceptance crit

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will define and build the CI/CD systems that qualify frontier models and the software stack running on OpenAI’s custom AI accelerators. Your work will make correctness, performance, and stability measurable on every change, from individual commits through production releases. This role spans model workloads, accelerator software, systems infrastructure, and developer productivity. You will establish scalable CI/CD, GitOps, and monorepo practices; design trustworthy regression and benchmarking pipelines; and partner with model, compiler, kernel, runtime, firmware, and hardware teams to shorten feedback loops without compromising production readiness. In this role, you will: Define the model CI strategy for frontier models running on OpenAI custom silicon and integrated accelerator systems. Build production CI/CD pipelines for functional regression, performance benchmarking, software stability, and release qualification. Design representative test matrices across models, configurations, hardware generations, software components, and deployment environments. Create reliable performance baselines, regression detection, bisect and triage workflows, and clear ownership for failures. Establish GitOps practices for reproducible configuration, promotion, rollback, auditability, and environment consistency. Shape monorepo architecture, dependency management, build and test boundaries, change validation, and developer workflows at scale. Develop scalable orchestration

About the Team OpenAI’s Hardware organization develops custom silicon and systems for advanced AI workloads. Our first-party accelerator team works across chip architecture, design, software, and systems to build the computing platforms that power frontier models. We are a small, dynamic team that values technical breadth, hands-on engineering, and creative approaches to building complex hardware. About the Role We’re looking for a SoC Engineer to help architect, design, and integrate OpenAI’s first-party AI accelerators. You will build the processor, interconnect, I/O, and platform infrastructure that connects our accelerator designs into complete, functional systems. This role combines architectural judgment with hands-on implementation. You’ll work closely with design, architecture, verification, and software teams throughout development, from defining subsystem requirements and integrating IP to pre-silicon validation, silicon bring-up, and post-silicon debug. You should enjoy stretching across domains, rolling up your sleeves, and doing the work needed to make a complex system function end to end. In this role, you will: Define and implement SoC architectures spanning embedded processors, AMBA interconnects, peripheral subsystems, PCI Express, Ethernet and die-to-die interfaces. Develop the microarchitecture and RTL design of subsystems supporting I/O and SoC functionality. Integrate Arm Cortex-M and Cortex-A processors, AXI/APB fabrics, and third-party controller IP, including the RTL and glue logic needed to connect these components. Develop reset and boot architectures, working with firmware and software teams to define sequencing, initialization, and survivability behavior. Incorporate debug, test, and security requirements into the SoC architecture and implementation, partnering with other silicon designers to make the silicon observable, testable, and secure. Drive PCIe and other I/O integration, including controller and PHY interfaces, high-speed SerDes,

About the Team OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. About the Role We are looking for an experienced Mechanical Engineer with 7+ years of experience in design of IT hardware from chip/package to system levels. You’ll work alongside experts in thermal, mechanical, electrical, software, and systems engineering to support the design, analysis, and validation of mechanical and thermal systems that ensure the reliability, efficiency, and longevity of mission-critical hardware. This position requires strong analytical skills, hands-on testing experience, and the ability to work in a fast-paced, cross-disciplinary environment. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Lead mechanical design for AI supercomputer product in the data center application Collaborate with the cross functional team to design and optimize thermal solutions for data center hardware, including chips, power modules, and system-level cooling architectures Collaborate with cross-functional teams to integrate thermal management strategies into hardware design, from concept to mass production Design and validate mechanical systems, including chassis, enclosures, cooling systems, and high-power connections, ensuring alignment with performance and reliability standards. Perform 3D modeling, FEA, tolerance analysis, and prototyping, ensuring manufacturability and a