Sr. Forward Deployed Engineer (FDE) - Communications, Media, Entertainment & Games

SpyCloud is on a mission to make the internet a safer place by disrupting the criminal underground. SpyCloud’s solutions thwart cyberattacks and protect more than 4 billion accounts worldwide. Cybersecurity is an exciting, evolving space, and being at the forefront of the fight to disrupt cybercrime makes SpyCloud a special place to work. If you’re driven to align your career with a fantastic mission, look no further! You are an experienced Cloud Ops Engineer who thrives in a fast-paced and AI-forward environment. You have a passion for innovation, solid design principles, and high-quality development. You excel at designing, improving, and maintaining secure, performant infrastructure and enjoy automating processes to ensure efficiency and scalability. You are a proactive problem solver with a strong understanding of system and networking concepts. What You'll Do: Infrastructure Design and Maintenance: Design, improve, and maintain secure, durable, and performant infrastructure to power APIs, AI operations, web applications, and data mining/ETL workflows to meet established SLAs. Collaborate with developers to bring new products and services into production. Automation and Monitoring: Automate testing, deployment, and monitoring of all products and services throughout the software development lifecycle. Continuously improve operational processes and apply best practices to ensure scalability, security, and availability. Security and Compliance: Proactively meet standards for information security and compliance, such as SOC 2/ISO27001/CMMC. Implement and uphold security measures across all infrastructure components. Requirements: Professional Experience: At least 5 years of professional experience in a Cloud Ops / Platform Ops / DevOps role maintaining production infrastructure, preferably supporting a highly available environment for a SaaS or cloud service provider. Technical Proficiency: Strong working knowledge of AWS services such as EC2, ECS or EKS, Lam

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we are building the next generation of AI and RISC-V compute. This role supports our CVP of Operations by turning priorities into execution, driving cross-functional programs forward, and making sure important work does not stall between teams. It is a high-trust role for someone who can bring structure to ambiguity, keep leaders aligned, and move quickly without creating noise. This role is hybrid, based out of Santa Clara,CA; Austin,TX; Boston,MA; or Toronto,ON. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are High-agency operator who moves seamlessly between executive-level priorities and day-to-day execution, owning end-to-end outcomes. Proven at driving complex cross-functional work across operations, finance, legal, recruiting, and business partners. Deep understanding of the semiconductor business, including development timelines, product portfolios, manufacturing, sales and operations planning, and financial investments. Clear, direct, and organized communicator who brings structure, follow-through, and sound judgment to fast-moving, ambiguous environments. Trusted partner to senior leadership, anticipating needs, press

POSITION SUMMARY: We are looking for a highly motivated Senior Research Associate with a strong focus on process optimization and improvements to join the Molecular Biology product development team, joining a group of scientists who are tasked with developing and advancing Natera’s oncology product portfolio. The Senior Research Associate performs research and/or development tasks in collaboration with others. Makes detailed observations, analyzes data, and interprets results. Investigates creates and develops new methods and technologies for project advancement. Maintains a high level of professional expertise through familiarity with scientific literature. PRIMARY RESPONSIBILITIES: Design, plan, and perform experiments geared towards the development of non-invasive prenatal tests and cancer detection tests. Autonomously and accurately plan and execute complex laboratory experiments Analyze data using advanced analytical tools Keep a detailed laboratory notebook; write protocols and experimental plans, and document results and scientific interpretations Contribute insight toward experimental findings and troubleshoot laboratory processes and protocols Communicate and discuss results with a multidisciplinary team including biologists, bioinformaticians, statisticians, software engineers, and managers Summarize work in research reports and laboratory meeting presentations Learn and understand the science behind ongoing research projects while simultaneously completing increasingly complex tasks. This role will have occasional access to PHI both in paper and electronic form and have occasional access to various technologies to access PHI (paper and electronic) in order to perform the job. The employee must complete training relating to HIPAA/PHI privacy, General Policies and Procedure Compliance training and security training as soon as possible but not later than the first 30 days of hire. Must maintain a current st

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent builds AI and RISC-V compute hardware that requires best-in-class design tools and intellectual property to compete globally. The Sr. Strategic Sourcing Manager, Engineering Infrastructure leads procurement strategy for the design ecosystem, owning vendor negotiations, IP licensing agreements, and tool sourcing that enable our worldwide engineering teams to innovate at speed. The role suits someone who takes ownership of complex, multidimensional deals, operates independently with minimal oversight, and commands credibility with vendor executives, internal stakeholders, and the C-suite. This role is hybrid or remote, based out of Santa Clara, CA; Austin, TX or Toronto, ON. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A strategic negotiator with 5+ years of experience sourcing complex technology (IP, design tools, or semiconductor components) in fast-paced environments Someone who builds trust-based vendor relationships and leverages them to unlock better terms, faster delivery, and innovative solutions A detail-oriented operator who thrives managing multiple concurrent deals while maintaining executive visibility and cross-func

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Design Verification Engineer to contribute to the unit-level verification of our RISC-V CPU front end—including instruction fetch, branch prediction, and surrounding fetch control structures. As a key individual contributor within our front-end DV team, you will focus on building testbenches, generating stimulus, and developing checkers for complex microarchitectural scenarios. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Front-End Experience: Solid background verifying CPU front-end blocks—such as instruction fetch, branch predictors (BTB, TAGE, RAS), instruction caches/TLBs, or decode—using SystemVerilog, UVM, and C++. Unit-Level Focus: Hands-on experience building clean, controllable unit testbench environments with precise stimulus and checking. Reusable Design: Pragmatic approach to building transactors, predictors, and scoreboards that can be reused across verification levels. Collaborative Problem Solver: Comfortable working alongside RTL designers to trace and fix misspeculation, redirect, and edge-case fetch bugs. What We Need Unit-Level Verifica

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team and lead the front-end RTL physical implementation team. Drive CAD flows on multiple process technologies while working closely with core micro-architects to refine CPU core configurations and optimizing PPA. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, RTL and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An expert in physical design practices used to optimize PPA Experienced in high-performance physical design. Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis. Skilled in synthesis, place and route tools including flows and physical design methodology. Background in CPU micro-architecture. What We Need Own front‑end physical implementation and PPA definition for a high‑performance RISC‑V CPU and CPU subsystem Work closely with microarchitects and RTL designers to “make the IP better” by optimizing frequency, power, and area