STAFF Engineer -DEG Layout

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. ASIC IP STA Engineer (6-10 Years) | DDR PHY / ONFI PHY / IO Expander Location: Bengaluru, India Experience: 6-10 Years Enducational Qualification : BE/B-Tech/M-Tech (EEE, ECE, Micron Electronics, VLSI) Key Requirements Member of the AMS IP Physical Design team , responsible for post-layout STA signoff and timing closure of high-speed interface IPs, with close collaboration across IP Design, SoC Synthesis, and SoC Physical Design teams throughout IP development and SoC integration. 6-10 years of experience in Static Timing Analysis (STA) with a proven track record of 4 &#43; successful tapeouts . Strong hands-on expertise with Cadence Tempus (preferred). In-depth experience in MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes. Experience working on high-speed Memory Interface IPs such as DDR PHY, ONFI PHY, IO Expander (IOE) , or similar high-performance interface designs. Strong understanding of timing constraints development, validation, and debug , including clocks, generated clocks, timing exceptions, and mode-specific constraints. Experience in Liberty (.lib) and ETM timing model generation, validation, correlation, and quality assessment . <span

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs

For over 20 years, Smartsheet has empowered teams to manage work seamlessly and scale solutions smarter. Now, in our most ambitious chapter yet, we are uniting human teams with AI agents. By orchestrating the work agents do best, automating manual tasks and uncovering insights at scale, we create the space for people to focus on what truly matters: judgment, creativity, and big thinking. That is magic at work, and it’s what we show up for every day. You Will: Data Architecture and Design: Designing and overseeing the architecture of scalable and reliable data platforms, including data pipelines, storage solutions, and processing systems Data Modelling and Management:Developing and implementing data models, ensuring data quality, and establishing data governance policies Data Pipeline Development: Building and optimising data pipelines for ingesting, processing, and transforming large datasets from various sources Performance Optimisation: Identifying and resolving performance bottlenecks in data pipelines and systems, ensuring efficient data retrieval and processing Technology Evaluation and Innovation: Staying abreast of emerging data technologies and exploring opportunities for innovation to improve the organisation’s data infrastructure Troubleshooting and Problem Solving: Diagnosing and resolving complex data-related issues, ensuring the stability and reliability of the data platform Data Security and Compliance: Implementing data security measures, ensuring compliance with data governance policies, and protecting sensitive data Perform other duties as assigned You Have: Bachelor’s or Master’s degree in Computer Science, Engineering, or a related field. 10+ years of experience in data engineering or a similar role. Enterprise SaaS software solutions with high availability and scalability Solution handling large scale structured and unstructured data from varied data sources Experience in building and maintaining data platform systems such as distributed compute,

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers.You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU verification or closely related digital design. You know high‑performance out‑of‑order CPU microarchitecture in depth. You work comfortably with RTL, waveforms, logs, and complex debug scenarios. You communicate clearly across design, DV, emulation, and post‑silicon teams. What We Need Plan and drive functional verification for CPU core features and complex microarchitectural scenarios. Develop UVM, assembly, and C/C++ based stimulus, functional models, and coverage for ISA, RISC-V extensions, and un-core components. Debug simulation and emulation regressions using RTL understanding, waveforms, and logs to identify and resolve issues efficiently. Build and enhance coverage models, testbenches, and debug infrastructure to improve verification quality and coverage closure. Collaborate with design, validation, and

Staff Engineer - Enterprise Search Overview We are looking for an experienced Enterprise Search Lead to build and optimize our multi-tenant enterprise search solution. This role focuses on creating scalable systems that integrate seamlessly with customer environments, leveraging cutting-edge AI and ML technologies. You will design and manage the enterprise knowledge graph, implement personalized search experiences, and drive AI-powered innovations to enhance search relevance and ITSM workflows. What You Will Do Build and structure our enterprise knowledge graph to organize content, people, and activity into meaningful relationships for better search relevance. Develop and refine personalized ranking models that adapt to user behavior and improve search results over time. Design ways to adapt AI language models to each customer’s data for enhanced accuracy and context. Explore innovative methods to combine LLMs with search engines for answering complex queries. Write clean, robust, and maintainable code that integrates smoothly with multi-tenant systems. Collaborate with cross-functional teams to align search capabilities with ITSM workflows. Mentor junior engineers or learn from experienced ones to grow as a technical leader. What You Should Have 5+ years of experience working on enterprise search products with AI/ML integration. Expertise in multi-tenant systems and securely integrating with external customer systems. Hands-on experience with tools like Elasticsearch, Solr, or similar search platforms. Strong coding skills in Python, Java, or equivalent languages. A passion for solving complex problems with AI and delivering intuitive user experiences. Important notice for candidates: Job scams are on the rise. Please keep these guidelines in mind when applying for any open roles at Atomicwork. Only apply through official Atomicwork channels. We do not use third-party agencies or individuals wh

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. What Makes This Opportunity Unique At Micron, we're not just offering a job; we're presenting a chance to be part of a team that develops the future of memory and storage solutions. As a Staff Engineer, ASIC STA in our Bengaluru office, you will have the opportunity to work with powerful technology and contribute to highly innovative projects. Your work will help us deliver flawless results and uphold our world-class standards! Job Responsibilities Proficient at Synthesis, Static Timing Analysis (STA), and Logic Equivalence Checking (LEC) Ability to understand and integrate new mixed signal complex IPs Expertise in developing constraints and timing models Manage synthesis to timing closure, ensuring all checks for silicon success Experience with hierarchical designs involving high-frequency clocks Proficient with scripting, automation, and EDA tools Proficiency with AI and AI-enabled workflows Solid understanding of low power builds involving multiple power domains Identify and meet requirements for critical paths of multi-GHz builds Collaborate effectively in multi-functional and globally dispersed teams Requirements M.S./M.Tech, BS/BE in Electronics or related field Minimum of 6&#43; years of relevant experience Proven ability to successfully implement complex builds Ambitious and determined to compete at a global level <