Wafer Architect

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s HBM design organization, building the test architectures that enable the most advanced memory products in the world. Our team works at the intersection of design, manufacturing, and silicon learning to make 3D‑stacked memory reliable at scale. We thrive on deep technical challenges and close collaboration across disciplines! As an HBM Design Architect, you will define how next‑generation HBM products are tested from wafer to system. This role is critical to ensuring quality, yield, and performance across complex multi‑die architectures. You’ll influence product success early, work hands-on with silicon, and partner closely with design, test, and manufacturing teams. Responsibilities: Define and implement end-to-end DFT architectures for HBM base die and DRAM die Develop DFT strategies for stacked-die, cube-level, and system-level test flows Architect test access mechanisms supporting wafer probe through final test Enable silicon observability for yield learning, debug, and failure analysis Collaborate across design, verification, layout, test, and manufacturing teams Minimum Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field Strong knowledge of scan, MBIST, JTAG, and boundary scan concepts Experience with wafer probe and fin

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s HBM design organization, building the test architectures that enable the most advanced memory products in the world. Our team works at the intersection of design, manufacturing, and silicon learning to make 3D‑stacked memory reliable at scale. We thrive on deep technical challenges and close collaboration across disciplines! As an HBM Design Architect, you will define how next‑generation HBM products are tested from wafer to system. This role is critical to ensuring quality, yield, and performance across complex multi‑die architectures. You’ll influence product success early, work hands-on with silicon, and partner closely with design, test, and manufacturing teams. Responsibilities: Define and implement end-to-end DFT architectures for HBM base die and DRAM die Develop DFT strategies for stacked-die, cube-level, and system-level test flows Architect test access mechanisms supporting wafer probe through final test Enable silicon observability for yield learning, debug, and failure analysis Collaborate across design, verification, layout, test, and manufacturing teams Leveraging AI for design quality

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. About Our Team: The Frontend Manufacturing Applications team develops and supports critical software platforms that enable Micron's wafer fabrication and assembly operations. Our team partners closely with manufacturing, product, and engineering organizations to deliver reliable, scalable solutions while advancing the adoption of AI-assisted engineering practices that improve developer productivity and software quality. Position Overview: As a Principal Software Engineer, you will serve as a technical authority responsible for defining architecture, engineering standards, and technical strategy for frontend manufacturing applications. You will lead the organization's AI-assisted engineering initiatives while delivering business-critical software solutions that improve manufacturing efficiency, reliability, and operational performance. Responsibilities: Lead architecture, design, and technical strategy for frontend manufacturing applications and platform modernization initiatives. Design, develop, and support production applications using technologies including .NET, C#, C++, Angular, Python, and related platforms. Establish and govern engineering standards, code review practices, and quality controls, including standards for AI-assisted software development. Evaluate, implement, and operationalize AI development tools, agentic workflows, and engineering productivity solutions across multiple tea

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next generation High Bandwidth Memory (HBM) architectures and circuit blocks. The HBM DFT Design Engineer is responsible for defining, designing, and integrating Design for Test (DFT) architectures for next generation High Bandwidth Memory (HBM) products. This role ensures robust test coverage across wafer, die, stack, and system in package (SiP) test stages while balancing performance, power, area, and manufacturing cost. The engineer works in a multi-functional manner with HBM build, verification, product engineering, test enablement, packaging, and external partners to deliver manufacturable, high quality HBM solutions. Responsibilities will include, but are not limited to: Define and implement HBM DFT architectures, including scan, MBIST, JTAG, boundary scan, TSV test, redundancy test, and at‑speed test structures. Develop DFT solutions for both base die and DRAM die, considering stacked‑die and cube‑level test requirements. Design and integrate test access mechanisms to support wafer probe, cube test, and SiP/system test flows. Collaborate with Product Engineering and Test Enablement teams to align DFT features with manufacturing test flows and cost targets. Support yield learning, failure analysis, and debug by enabling observability and controllability in silicon. Work closely with logic, analog, layout, verification, and physical design teams to ensure DFT is

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Role Summary The SMTS acts as a technical authority in 3D NAND cell film development, setting strategic direction and leading multi-functional initiatives to drive department-wide impact by architecting solutions, accelerating innovation adoption, influencing technical standards, and mentoring engineers to elevate technical excellence. Defines technical strategy and drives cross-org adoption; leads complex problem solving across process/hardware/device interactions with no yield trade-off; builds the SME pipeline through structured mentorship. Main Responsibilities Define technical strategy; architect solutions; influence technical standards and drive process improvements; lead advanced process development, fixing, and integration. Integrate unit processes into full cell packages and validate device/process linkages via wafer-level electricals. <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Product Quality Engineer, you are responsible for ensuring the stability and reliability of semiconductor manufacturing processes. This role involves defining standard operating procedures, applying statistical tools, and supporting audits to maintain high product quality standards. Additionally, the Principal Product Quality Engineer is a strategic leader responsible for architecting and driving global quality frameworks across multiple manufacturing sites. This role uses advanced engineering expertise, data analytics, and multi-functional collaboration to ensure process stability, product reliability, and continuous improvement at scale. You will influence global strategy and drive innovation. Responsibilities: Lead multi-functional and cross-site teams to resolve complex quality issues, driving global alignment and continuous improvement. Develop and implement global quality management systems in partnership with other Micron manufacturing facilities. Support the NPI qualification, PG/PTS yield improvement, Burn and module dpm reduction, defense line 4 enhancement and shift-left improvement Cover critical SWRs and RAR risk assessment, Fab Excursion-affected materials and RMA management. Monitor and report on critical quality metrics, including DPM, yield variation, and reliability performance. Supervise Wafer Level Reliability (WLR) and Wafer Level Burn In (WLBI)