Advanced Boom Barrier And Sliding Gate Solutions By Hexaworld Jobs

Principal Engineer - Dry Etch, Operations Central Teams - Advanced Development Team — Hiroshima - Fab 15, Japan. Apply via Workday.

Principal/Senior Engineer, APTD CEM - Advanced Packaging Integration Engineering — Fab 10A, Singapore. Apply via Workday.

Staff Product Engineer (GenAI, AI/ML & Advanced Data Analytics) — Fab 10A, Singapore. Apply via Workday.

Ready to do the most impactful work of your career? At Coinbase , we are uncompromising on our mission to increase economic freedom. The bar is high, the environment is intense, and we like it that way. This isn't a place for complacency, it’s a place to be pushed past your perceived limits. If you're ready to build the future of finance alongside people who refuse to settle for "good enough," you belong here. Coinbase is a remote-first, but not remote-only company. Expect to get together quarterly for intense in-person working sessions called “surges.” learn more about working at Coinbase . As a Staff Software Engineer, Frontend on the Advanced Trading team within the Consumer & Business group, you'll lead the front-end technical strategy for Coinbase Advanced, our trading platform for experienced traders. You'll own the performance, reliability, and scalability of our web and mobile trading clients, driving low-latency interfaces that serve traders across multiple instrument types. This is a high-impact role at the intersection of crypto, trading infrastructure, and consumer product, where your technical leadership will shape both the platform and the engineering team building it. What you'll do: Own the front-end technical roadmap for Coinbase Advanced, defining architecture decisions that enable a reliable, scalable trading platform across web and mobile Drive measurable performance improvements across rendering, network efficiency, and state management to deliver a low-latency trading experience Lead complex, multi-quarter technical initiatives end-to-end, setting and enforcing high standards for code quality, system design, and engineering rigor Strengthen the engineering team through hands-on mentorship of senior engineers, elevating technical decision-making and fostering growth across the subteam Partner with Product and Engineering leadership to translate business priorities into actionable technical plans and ship high-impact features Shap

Wet Process DMTS/SMTS, Process Development SG, Advanced NAND — Fab 10N/X, Singapore. Apply via Workday.

Dry Etch MTS/Principal Engineer, Process Development SG, Advanced NAND — Fab 10N/X, Singapore. Apply via Workday.

Senior Engineer, Process Integration, Advanced NAND — Fab 10N/X, Singapore. Apply via Workday.

Dry Etch MTS/Principal Engineer, Process Development SG, Advanced NAND — Fab 10N/X, Singapore. Apply via Workday.

Wet Process - Senior Engineer, Process Development SG, Advanced NAND — Fab 10N/X, Singapore. Apply via Workday.

Photolithography Staff/Sr Engineer, Process Development, Advanced NAND — Fab 10N/X, Singapore. Apply via Workday.

Principal Engineer, Films/Diffusion - Procurement and Operations Central Team Advanced Development — Hiroshima - Fab 15, Japan. Apply via Workday.

Principal Engineer, Region E, Operations Central Teams Advanced Development Team — Hiroshima - Fab 15, Japan. Apply via Workday.

Senior/Staff/Principal/MTS Engineer, Etch - Procurement and Operations Central Team Advanced Development — Boise, ID - Main Site. Apply via Workday.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer who will contribute to the physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout. You will partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs. Along the way, you will build end-to-end ASIC expertise while learning from experienced engineers across the chip development process. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An engineer excited to work on high-performance designs for industry-leading AI/ML architectures. A collaborative problem solver who enjoys working with experienced engineers across ASIC disciplines. Grounded in logic design fundamentals and gate- and transistor-level implementation. Curious about how early architectural and RTL decisions shape physical implementation and final chip quality. What We Need A BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a relat

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer with a strong background in static timing analysis (STA). In this role, you will help converge multi-million-gate designs on advanced process nodes and partner with cross-functional teams through final signoff and tapeout. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A physical design engineer with 8+ years of experience in STA, timing closure, and advanced-node design implementation. Experienced with timing flows, constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding, and final signoff. Skilled in writing and debugging SDC constraints, creating ECOs, developing closure strategies, and analyzing worst-case corners. A strong collaborator and communicator who can drive results across distributed, cross-functional engineering teams. What We Need Drive timing convergence across blocks, partitions, sections, and top-level designs; generate and validate timing models and publish results. Analyze timing violations, develop and propagate fixes, debug timing-flow issues, and