Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our Vision Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever. Micron is advancing a historic $15 billion investment in semiconductor manufacturing in Boise, Idaho, with DRAM production planned for the second half of the decade. As a global leader in memory and storage solutions, Micron is investing more than $150 billion worldwide over the next decade to expand leading-edge manufacturing capabilities and drive innovation across the semiconductor industry. Join the Boise expansion team and help build the future of semiconductor manufacturing. You will work alongside experienced engineers to develop advanced processes, solve complex manufacturing challenges, and support the production of technologies that power everything from artificial intelligence to next-generation computing systems. Position Overview As a PCVD Process Engineer , you will contribute to the development, optimization, and sustainment of semiconductor manufacturing processes. You will gain hands-on experience in a state-of-the-art fabrication environment, partnering with teams to improve yield, quality, reliability, and productivity. This role offers an outstanding opportunity to apply engineering fundamentals, build technical expertise, and develop a career in advanced semi

Lead RF Systems and Defense Engineer- HP IQ Description - Who We Are HP IQ is HP’s new AI innovation lab. Combining startup agility with HP’s global scale, we’re building intelligent technologies that redefine how the world works, creates, and collaborates. We’re assembling a diverse, world-class team—engineers, designers, researchers, and product minds—focused on creating an intelligent ecosystem across HP’s portfolio. Together, we’re developing intuitive, adaptive solutions that spark creativity, boost productivity, and make collaboration seamless. We create breakthrough solutions that make complex tasks feel effortless, teamwork more natural, and ideas more impactful—always with a human-centric mindset. By embedding AI advancements into every HP product and service, we’re expanding what’s possible for individuals, organisations, and the future of work. Join us as we reinvent work, so people everywhere can do their best work. About The Role HP IQ's Wireless Technology Team works cross-functionally with Electrical Engineering, Software, Mechanical Engineering, Product Design, Industrial Design, Program Management, and Operations to develop next-generation wearable and AI-connected products. As a Lead RF Systems & Desense Engineer, you will own the RF system architecture from concept through mass production. You will lead RF integration across Wi-Fi, Bluetooth, UWB, NFC and emerging wireless technologies while driving RF desense, coexistence, and wireless performance for highly integrated products. <span style=

Work Flexibility: Onsite As the Manager, Quality Assurance , you will lead quality assurance activities that support product quality, process performance, audit readiness, and continuous improvement across site operations. Working closely with Operations, Global Quality, Regulatory Affairs, and supplier partners, you will help ensure quality systems remain effective, compliant, and aligned with business objectives. This role is Onsite in Mahwah, New Jersey . What You Will Do Lead the Quality Assurance team, providing technical guidance and quality oversight across manufacturing and operations, supports functions to drive continuous improvement and compliance. Partner with site leadership to ensure products consistently meet customer expectations, regulatory requirements, and applicable quality standards. Develop, coach, and retain a high-performing team while fostering a culture of inclusion, accountability, collaboration, and employee engagement. Drive quality system compliance by partnering with functional leaders to establish, communicate, and maintain quality standards, requirements, and responsibilities. Lead site readiness activities and support internal, corporate, notified body, FDA, and other regulatory audits and inspections. Oversee the management of nonconforming products, product and process deviations, risk assessments, corrective actions, and preventive actions to ensure effective resolution and compliance. Monitor and improve Quality performance indicators, including NCR, CAPA, compliance, and operational quality metrics, and implement corrective actions for adverse trends. Support the development and execution of local and global Quality Operations strategies that improve product quality, operational efficiency, risk management, and regulatory compliance. <

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Responsibilities and Duties We are seeking a highly skilled System Tests & Diagnostics Engineer to develop, extend, and integrate specialized silicon validation and diagnostics tools for next-generation AI SoCs. Unlike traditional validation roles focused on executing test plans, this position is responsible for developing the diagnostic software and stress tools that expose hardware failures, characterize silicon behavior, and improve platform observability throughout bring-up and validation. You will work closely with Arm engineers to understand and extend existing diagnostics technologies while developing Graphcore-specific capabilities for future AI hardware. Role Summary You will work with existing Arm-developed diagnostics technologies and extend them to support Graphcore's next-generation AI silicon. You will be responsible for developing system-level diagnostics and stress tools that integrate with an existing framework to detect data integrity, computational correctness, performance, and reliability issues across CPUs, AI accelerators, memory, storage, PCIe, firmware, BMC, and other platform components. Examples include silent data corruption (SDC) tests, power transient stress tools, and platform diagnostics, with opportunities to develop new diagnostics as future hardware capabilities evolve. This role requires close collaboration with hardware architects, firmware enginee

Job Details: Job Description: The Thin Films Senior Process Engineer will support PVD, CVD, and ALD technologies for dielectric and metal thin-film deposition in a high-volume manufacturing environment. Key Responsibilities Apply advanced expertise in thin-film deposition processes to drive continuous improvement in process performance, sustainment, and technology development. Collaborate with upstream and downstream partners to deliver manufacturing improvements through strong cross-functional engagement and stakeholder management. Own manufacturing processes and/or equipment, ensuring achievement of key performance indicators (KPIs) including safety, quality, cost, productivity, defect reduction, and yield improvement. Develop and execute strategic plans for complex projects, coordinating timelines and dependencies across multiple teams and initiatives. Support manufacturing capacity expansion and technology transfer activities to enable successful ramp-to-volume production. Partner with equipment vendors and cross-functional stakeholders to troubleshoot technical challenges, improve tool performance, and enhance operational efficiency. Lead process development initiatives that support current and next-generation high-volume manufacturing technologies. Design and optimize excursion prevention and detection systems to strengthen process control and minimize manufacturing risk. Lead equipment installation, conversion, qualification, and readiness activities during factory ramps, ensuring all tools are deployed safely, on schedule, and in compliance with quality and manufacturing standards. Drive root cause analysis and implement corrective actions to resolve process and equipment-related issues while improving overall manufacturing stability and performance. <p st

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum IC Substrate Package Layout Design Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for design of large form factor IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Design of IC substrates using Siemens Xpedition IC package design software - Work closely with stakeholders to meet design requirements - e.g., receive feedback from silicon testchip, signal integrity (SI), power integrity (PI), thermal simulation, and system integration engineers - Deliver and disseminate design milestones to stakeholders - Design validation and verification; including DRC and LVS - Advanced packaging design integration (2.5D and 3D) with IC substrate - Tapeout of designs with substrate suppliers in collaboration with Intel substrate teams - Communicate designs in presentations and relevant documentation - Stay curre

Job Details: Job Description: Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below. Life at Intel The Role and Impact As a SoC Power Thermal Performance Validation and Optimization Engineer, you will play an essential role in ensuring Intel's products achieve optimal power, thermal, and performance benchmarks at the system-on-chip (SoC) level. In this position, you will develop and execute validation methodologies, optimize hardware/software solutions, and perform SoC-level debugging to address power, thermal, and performance challenges. Your contribution will directly impact Intel's ability to deliver competitive, high-performing products to market. Business Group This role is part of Intel's Data Center Group (DCG), which focuses on designing innovative solutions to power the next generation of computing platforms for data centers. As a member of the PTP PreSi Correlation Solution team, you will contribute to shaping the development and validation processes for cutting-edge technologies, ensuring Intel meets and exceeds industry standards for performance and efficiency. Key Responsibilities: Develop and execute SoC-level power, thermal, and performance validation and

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum Packaging Signal/Power Integrity (SI/PI) Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for modeling and simulation of various packaging solutions from silicon redistribution layers to IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Modeling and simulation of packaging hardware including redistribution layers (e.g., interposers, RDLs), IC substrates, and silicon testchip routing - Work closely with stakeholders to meet design requirements - requirements come from both theory and hardware teams. In some pathfinding projects, you will be asked to participate in creating requirements and novel packaging hardware. - System-level modelling and simulation; end-to-end simulations to ensure designs meet system-level requirements - Deliver and disseminate design milestones to stakeholders - Communicate designs in pr

About the Team Consumer Monetization builds the experiences and systems that power how customers purchase and pay for OpenAI products. Our scope spans purchasing flows, payments, subscriptions, and billing, along with the shared capabilities that support new products, offers, and distribution channels. We own both customer-facing experiences and the underlying platforms that power them. We partner closely with Product, Design, Growth, Data Science, and engineering teams across OpenAI to make purchasing effective and reliable, and new offerings easier to launch and monetize. About the Role We’re looking for experienced Staff+ engineers with deep iOS or Android expertise and demonstrated experience contributing beyond mobile to frontend web or backend development. You’ll shape and build purchasing and subscription experiences across mobile applications, web, and supporting product APIs. The work spans improving conversion, performance, and reliability, building reusable components, and enabling new product launches. You’ll combine product judgment with technical depth to set direction, lead initiatives across teams, and remain hands-on through implementation and delivery. Approximately 50% of the work will initially be native mobile development, with the remainder across web and product APIs. We’re looking for engineers who enjoy working across the stack and have concrete examples of doing so professionally. Depth in either iOS or Android is required; experience in both is not required. This role is based in San Francisco, with three days per week in the office. In this role, you will: Architect and build purchasing and subscription experiences across native mobile, mobile web, and supporting product APIs. Partner with Product, Design, and Growth to identify customer needs, prioritize improvements, and shape technical direction for purchasing experiences. Improve conversion, performance, and reliability through experimentation, product analytics, and customer insights

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron in Boise, Idaho has a current need for a Senior or Staff R&D Photolithography Materials Engineer . Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an R&D Photolithography Materials Engineer at Micron Technology Inc., we are responsible for photolithography material selection and optimization for advanced memory devices. In this position, you will develop new technology and photo materials that meet device requirements and integrate new technology into manufacturing processes. This work could include photo materials for any photo processes including hardmasks and resists for I-line (365nm) through EUV (13.5nm). Additionally, you will address process and materials issues with pilot manufacturing and work on continuous improvements for manufacturability. Job Responsibilities: Lead long-term resist screening projects. Define success criteria with process owners, evaluate multiple rounds of design of experiments (DOEs) with suppliers, and identify top materials for detailed evaluation on devices in technology development. Broad knowledge and experience in photoresist chemistry with an ability to direct material optimization and development with our suppliers Work in a cleanroom, follow safety proc

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsible for understanding the processes used to assess and mitigate risks related to the introduction of new package technologies so that you can improve efficiency and effectiveness by implementing automation, data analysis and machine learning/AI solutions. Set up data bases, develop data ingestion pipelines, and implement automated data analysis and reporting tools. Support problem solving and risk assessment for internal or customer quality issue by pulling and analyzing data. Contribute to the advancement of technology at Micron through mentoring, publishing technical papers (internal and external), and developing innovative solutions to challenging problems. Implement Automation, Data Analysis, and AI Solutions. Collaborate with Engineering teams to Map Package DDQA processes and data streams. Set up and optimize databases and develop solutions to improve efficiency and effectiveness. Understand the needs of internal customers and develop solutions. Support Problem Solving and Risk Assessment for Quality Issues. Pull relevant product information, manufacturing data, and reliability data based on given problem statements. Determine the appropriate dataset and treatment required to answer questions posed by problem solving teams. This could include producing data visualizations, machine learning models, statistical inferences, and web applications. Provide recommendations about root cause findings and product risk, based on data analysis. Collaboratively Communicate Findings and Best Practices. Share best practices with global teams to enable a cultur

Experienced or Senior Digital Design Engineer Company: The Boeing Company Boeing Defense, Space & Security (BDS) seeks a Digital Design Engineer to join our team in Huntsville, AL and play a vital role in the Patriot Advanced Capability-3 (PAC-3) program, one of the world's most advanced air and missile defense systems. This is your opportunity to work in a dynamic environment where your skills will directly contribute to protecting critical assets and ensuring mission success. If you are passionate about defense technology and want to make a real impact, we want to hear from you! Position Responsibilities: Design high speed digital circuits and perform signal integrity analysis Focus on electronic systems and electrical design, simulation and verification/validation testing of high-speed printed circuit boards (PCB) throughout full product development cycle Providing design guidelines and support for system architecture design, board layout, product bring-up, debug, validation, and factory builds This position requires obtaining a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim U.S. secret clearance Pre Start and final U.S. secret clearance Post Start is required. Basic Qualifications (Required Skills/Experience): Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement 3 or more years of related work experience Experience in digital circuit design Preferred Qualificatio

The SCG Architecture team is hiring a Senior Power Integrity Co-Design Engineer to architect and deliver di/dt mitigation across silicon, package, board, and platform. This role bridges architecture, silicon, and platform — translating product noise targets into shipped specifications, and feeding silicon findings back into the next generation's build. Success in this role requires strong systems thinking and a willingness to accept ambiguity. It also requires the ability to apply AI as a force multiplier while maintaining rigorous engineering judgment. What you'll be doing: Architect voltage-noise mitigation across the full stack — silicon, package, board, platform — and own the codesign trade-offs between them. Co-design noise features with Speed, Power, Reliability, Circuit Design , Power-Arch, ASIC, and platform teams. You're the connective tissue across the codesign web. Work with other team members to define product-level voltage noise targets, drive them to closure, and sign them off at shipment. Build and take ownership of the Sim-to-Si correlation methodology for noise. You know when a model is lying and when silicon is. Model and prototype next-gen noise features — transient sense, droop response, mitigation IP, and codify them so every future program inherits them. Lead show-stopper noise bugs during bringup. The critical issues stop with you. Drive architecture-level codesign tradeoffs across V/F Power Noise Reliability Thermal (Noise-Variation) and (Noise-to-Closure) boundary work, where the highest-leverage innovation lives. What we need to see: BS / MS / PhD in EE, CE, or related (or equivalent experience). 5&#43; years in silicon power integrity, voltage noise, or PDN. Deep expertise in at least one of

Location: Remote (U.S.) Clearance: U.S. Citizen or Permanent Resident Required with the ability to obtain a Public Trust Salary Range: 110K – 125K LTS is seeking a Senior Security RMF Engineer to join a cybersecurity transformation surge team supporting the VA.gov Platform. This role will serve as the bridge between VA security/RMF requirements and the engineers responsible for implementing those requirements across VA.gov. The Senior Security / RMF Engineer must understand how security controls are implemented in modern cloud infrastructure and software delivery environments and be able to translate control deficiencies, authorization requirements, and security risks into actionable engineering work.This is not intended to be a documentation-only compliance role. This individual will work closely with DevSecOps engineers and the existing VA.gov Platform ATO/security team to assess the current security posture, address gaps in VA.gov's Critical Controls, support ATO/cATO readiness, improve authorization artifacts, and automate evidence and control assessment wherever possible. The PWS specifically describes the desired model as one in which ATO/RMF documentation confirms security rather than defines it, with success measured through risk reduction and security outcomes rather than paperwork completeness. What You’ll Do: Assess VA.gov Platform compliance with the 18 Critical Controls identified by VA and help establish a baseline of current implementation and remaining gaps. Perform security reviews, gap analyses, and risk assessments across VA.gov Platform infrastructure, pipelines, applications, and component systems. Support ongoing ATO and cATO readiness for the VA.gov Platform authorization boundary. Develop, update, and maintain RMF and authorization artifacts, including System Security Plans (SSPs), control narratives, POA&Ms, Business Impact Analyses (BIAs), Privacy Threshold Analyses (PTAs), and supporting evidence. Evaluate identified

Job Details: Job Description: Intel India Customer Engineering Team is in a mission to create successful Original Design Manufacturers (ODMs) from India across their customer base. We are seeking a Hardware Board Design Engineer specializing in Power Delivery design and debug experience to help Intel customers design and debug their hardware platforms based on Intel Core and Atom CPUs. Qualifications: • Education : Bachelor's or Master's degree in Electronics/Electrical Engineering or related field • Experience : 7-12 years of industry experience (preferably 5-6 years designing and debugging hardware boards with Power Delivery focus using Intel Core/Atom CPUs) • Power Delivery Expertise : Deep understanding of system Power Delivery requirements and familiarity with Intel Core/Atom processor Power Delivery guidelines including IMVP specifications and PDN analysis • Circuit Design : Extensive experience with Buck, Boost, and Multi-phase Power Delivery Network design, including control loop understanding and very high current/low-voltage power delivery design • Design Tools : Proficiency in schematic capture using ind