Firmware Engineer Bios Uefi Jobs

NVIDIA is seeking a strong technology leader to manage our Server Software Technical Program Management (TPM) team. This role is at the cross-section of execution and strategy, leading a team of Senior TPMs who drive the firmware and system software for NVIDIA's next-generation server platforms like DGX, MGX, and HGX. These platforms bring together the full power of NVIDIA GPUs, NVLink, InfiniBand networking, Grace CPUs, and our optimized AI/HPC software stack. This deep technical leadership role focused on the Software Development Processes that brings new server hardware to life. What you'll be doing: Lead a team of TPMs driving the technical software and firmware execution for NVIDIA's NPI (New Product Introduction) and sustaining engineering teams. Drive the end-to-end SDLC for low-level server components, including firmware (BMC, UEFI/BIOS), drivers, and system management software, ensuring alignment with hardware schedules. Collaborate closely with NVIDIA product management and hardware engineering teams to define release plans and program objectives. Build a strong connection and feedback loop between sustaining and NPI engineering teams to improve product quality and development velocity. Lead process improvement initiatives and help propagate SDLC standards across multiple engineering and TPM organizations. You will have the opportunity to interact with diverse technical groups, spanning all organizational levels. What we need to see: Bachelor of Science (or equivalent experience) or Master of Science degree in Computer Science, Electrical Engineering, or related field. 12+ overall years of experience developing and leading complex low-level or system software projects. and 7+ years of experience in a people management role. Deep understanding of system a

Distinguished Technologist - Principal Architect, Platform Security and Firmware Systems Description - HP is seeking a senior technical leader to serve as a lead architect for hardware rooted Platform Root of Trust for HP's commercial PC platform. In this role, you will be responsible for envisioning, defining, and driving the architecture of hardware, firmware, software, and cloud-integrated security capabilities that protect HP commercial PCs from current and emerging threats. You will also work across the hardware and security architecture teams, collaborate with HP's Security Research Labs, Firmware (BIOS) team, our security business that creates and deploys industry leading enterprise security and manageability solutions, product management, manufacturing, supply chain, customer enablement, and field organizations to create cohesive system solutions that deliver unique customer value. This position requires deep expertise in embedded systems, platform firmware, hardware, security, device manageability, and PC system architecture. The role also requires the ability to translate complex technical capabilities into customer-relevant value propositions and to influence internal and external stakeholders without relying solely on formal authority. Responsibilities Serve as principal architect for HP Endpoint Security Controller roadmap, associated hardware and firmware based capabilities, cryptographic identity, attestation, secure communication, event logging, and future controller generations. Define and evolve HP Sure Start architecture and related firmware resilience capabilities, including hardware-enforced firmware authenticity, recovery, update, and protection mechanisms. Drive secure BIOS and firmware configuration management strategies, including HP Sure Admin ecosystem capabilities, key management, zero-touch provision

NVIDIA's invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern deep learning - the next era of computing - with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. Today, we are increasingly known as &#34;the AI computing company.&#34; We're looking to grow our company and establish teams with the most thoughtful people in the world. We are looking for an excellent Senior Engineering Manager to lead a large firmware engineering organization delivering end-to-end manageability firmware for NVIDIA's next generation Data Center Compute Systems. This role owns HGX product line and OpenBMC-based management firmware and MCU firmware components in data center platforms, including architecture, execution, quality, reliability, telemetry, and customer readiness. We are seeking an experienced senior leader with strong technical depth, broad system perspective, and a proven ability to lead large teams through complex product cycles. This role is onsite in Santa Clara, CA, USA. If you're creative and autonomous, we want to hear from you! What you'll be doing: Lead a large firmware engineering organization delivering OpenBMC based firmware and MCU firmware for next-generation Data Center Compute Systems. Own HGX platform as a lead for Firmware and System software readiness working across the organization. Define and drive the long-term firmware roadmap, balancing architectural innovation with product execution and delivery milestones. Drive architecture strategy across BMC, MCU, platform software, manageability, health management, and data center firmware interfaces. <spa

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE As the Engineering Manager for Drive Qualification, you will lead a high-performing Bangalore team dedicated to validating Everpure-developed SSDs across performance, reliability, and firmware maturity. In this impactful leadership position, you will own the end-to-end validation strategy for hyperscale and datastore programs, establishing a center of excellence for system-level robustness. Partnering closely with cross-functional firmware, hardware, and analytics teams globally, your mission is to deliver comprehensive qualification coverage that ensures our enterprise storage platforms launch with ultimate confidence and quality. WHAT YOU’LL DO Lead and Scale the Team: Coach, mentor, and grow a multi-level validation engineering team, building a culture of ownership, clear domain expertise, and continuous career development. Drive Validation Strategy: Own the execution roadmap for core qualification domains (including PCIe, NVMe/OCP, and power-loss robustness) across critical milestone gates from engineering samples to final product release. Foster Cross-Functional Alignment: Partner with global hardware, firmware, and program management stakeholders to align on test coverage, coordinate issue triage, and deliver clear risk assessments that dictate release readiness. Advance Automation and Infrastructure: Champion the expansion of Python and Linux-based automation frameworks, regression infrastructure, and data

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE You will be the pivotal, end-to-end owner driving the product lifecycle for our cutting-edge data center storage solutions. Your mission is to translate product vision into Mass Production (MP) reality, managing all aspects of the hardware (Mechanical and Electrical Engineering) and the full software stack (firmware, OS). This highly visible role requires you to orchestrate global, cross-functional engineering, manufacturing, and supply chain teams while leading executive-level phase gate reviews to ensure our products deliver optimal performance and compliance, on time and on budget. WHAT YOU'LL DO End-to-End Release Ownership: Own the overall release plan, including scope, milestones, and dependencies. You’ll be the primary point of contact for release lines across Product, Engineering, QA, and Security. Strategic Program Leadership: Manage multiple concurrent workstreams involving cross-functional stakeholders. You will own the "big picture," ensuring that high-level technical architecture aligns with execution. Release Integrity: Own release branch health metrics. You’ll lead bug scrubs, triage critical issues, and define the criteria for merging new payloads (leveraging your experience with Git-based workflows). Operational Excellence: Drive the Product Lifecycle (PLC) phase exit reviews (Phases 0–3). You will define exit criteria, ensure they are met, and formally drive approvals. Risk & Conflict Resolut

About Graphcore Graphcore is a global leader in artificial intelligence computing systems. We design advanced semiconductors and data center hardware that deliver the specialized processing power needed to advance AI while improving the efficiency required for broad adoption. As part of SoftBank Group, Graphcore belongs to a family of companies developing some of the world’s most transformative technologies. Our new AI Engineering Campus in Austin will play a central role in building the future of AI computing. The Opportunity We are seeking a system validation engineering intern to help drive server blade and rack validation efforts for next-generation AI infrastructure hardware systems. This role focuses on post-silicon system validation across the full lifecycle of server hardware systems, ensuring functional and performance meets product objectives. You will help drive end-to-end blade and rack validation including development, execution, and debug while collaborating across silicon, firmware, systems, and platform teams. The Blade and Rack Validation team is responsible for ensuring system readiness and quality at scale. The team works cross-functionally with firmware, silicon, and system engineering teams to validate complex AI compute platforms. Type: 12-week summer internship Timing: May - August (exact dates to be confirmed) Commitment: Full-time What You’ll Do Help drive and execute post-silicon validation goals of AI compute blades and racks including testcase planning, development, and automation Help drive validation testcase execution and system debug against program achievements and report validation progress and risks. Drive provisioning and integration of system components (SoC FW, BMC, RMC, OS) for rack-level readiness Triage test failures, collect debug data, and collaborate on root cause analysis. Track validation coverage and continuously improve test processes and infrastructure. What You’ll Bring Working towards a Bachelor's

Job Details: Job Description: About the Role The Client Computing and Physical AI Group (CCG) is shaping the future of AI-enabled computing experiences. We are seeking a highly motivated Senior Customer Solutions Architect, Graphics & AI to drive customer adoption of Intel's graphics and AI technologies across next-generation client platforms. In this role, you will serve as a trusted technical advisor to strategic customers and ecosystem partners, helping define, architect, validate, and optimize innovative graphics and AI solutions. You will work across hardware, firmware, software, and platform teams to translate customer requirements into scalable product solutions while influencing future technology roadmaps. This position blends deep technical expertise, customer engagement, cross-functional leadership, and innovation to accelerate the deployment of Intel AI and graphics technologies. What You’ll Do Key responsibilities will include but not limited to: Be the center point of contact for technical collaborations with the customer and with various internal teams. Own end to end architecture of customer solution in alignment with product and IP architectures, and its translation to product requirements. Co define test vehicle and validation strategy, and collaboratively manage the execute schedule and resource negotiation. Drive technology tradeoff decisions ensuring customer needs are met, along with satisfying standards and specifications, and execution reality. Be the customer voice and collaborate heavily with internal execution teams and manage customer dashboards. Participate and contribute in identifying critical technology solutions for future product needs and influence roadmap.

Solution Architect Program Manager Description - Job Summary The Solution Architect Program Manager is responsible for driving advanced technology solutions from early concept through architecture definition, proof of concept, productization planning, system integration, validation, and launch readiness. This role combines deep technical capability with disciplined program execution to ensure that innovative concepts are translated into clear scope, committed deliverables, product milestones, and launch timelines. This position requires strong solution architecture judgment, structured planning, and cross-functional leadership across engineering, product, hardware, firmware, software, validation, security, operations, and external partners. The role owns the bridge between concept feasibility and production execution by defining requirements, aligning stakeholders, managing schedules, resolving technical dependencies, tracking risks, and maintaining readiness documentation required to deliver solutions on product milestones and market launch commitments. Responsibilities Drive end-to-end solution programs from concept exploration, business and technical feasibility, architecture definition, POC execution, productization planning, system integration, validation, and launch readiness. Translate ambiguous innovation concepts into clear solution scope, use cases, requirements, architecture assumptions, success criteria, milestones, resource needs, and execution plans. Own integrated schedules that align engineering deliverables with product development checkpoints, POR decisions, validation gates, manufacturing readiness, and launch timeline commitments. Partner closely with product management, system architecture, hardware, firmware, software, security, validation, operations, and external suppliers to manage dependenci

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE As a key contributor within the Drive Qualification Center of Excellence, you will ensure the performance and reliability of Everpure-developed SSDs for hyperscale and enterprise environments. You will partner with firmware and hardware teams to validate mission-critical storage components, transforming complex technical requirements into robust validation frameworks. Your mission is to guarantee that our storage solutions exceed global customer expectations through rigorous system-level testing and data-driven analysis. WHAT YOU’LL DO Design and deliver automated validation suites that stress-test PCIe, NVMe, and OCP compliance, ensuring firmware maturity and hardware robustness for the Everpure Platform. Drive technical root-cause analysis for complex failures across firmware and system layers, utilizing telemetry and logs to resolve performance or data integrity bottlenecks. Own and scale the regression infrastructure , improving test repeatability and coverage to accelerate the qualification cycle for next-generation NAND technologies. Collaborate with cross-functional engineering teams to provide clear risk assessments and quality metrics, directly influencing product readiness and release timelines. Develop custom validation tools and scripts in Python to automate the characterization of drive-level behavior under power-loss, snapshot, and high-volume scenarios. WHAT YOU BRING Deep Technical Expertise: Profi

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE As a key contributor within the Drive Qualification Center of Excellence, you will ensure the performance and reliability of Everpure-developed SSDs for hyperscale and enterprise environments. You will partner with firmware and hardware teams to validate mission-critical storage components, transforming complex technical requirements into robust validation frameworks. Your mission is to guarantee that our storage solutions exceed global customer expectations through rigorous system-level testing and data-driven analysis. WHAT YOU’LL DO Design and deliver automated validation suites that stress-test PCIe, NVMe, and OCP compliance, ensuring firmware maturity and hardware robustness for the Everpure Platform. Drive technical root-cause analysis for complex failures across firmware and system layers, utilizing telemetry and logs to resolve performance or data integrity bottlenecks. Own and scale the regression infrastructure , improving test repeatability and coverage to accelerate the qualification cycle for next-generation NAND technologies. Collaborate with cross-functional engineering teams to provide clear risk assessments and quality metrics, directly influencing product readiness and release timelines. Develop custom validation tools and scripts in Python to automate the characterization of drive-level behavior under power-loss, snapshot, and high-volume scenarios. WHAT YOU BRING Deep Technical Expertise: Profi

NVIDIA builds the silicon behind AI, accelerated computing, and graphics. Every watt of performance and every degree of thermal headroom traces back to decisions made in power, performance, and thermal architecture. We are the Silicon Co-Design Group (SCG). We identify, own, and drive system-level co-design ideas. We start with initial concepts and advance to product differentiation across NVIDIA's roadmap. We are hiring a Principal System Power Management and Performance Architect who operates at the ambiguous boundary where workload behavior, silicon capabilities, firmware policies, and platform constraints collide, and who turns that ambiguity into architecture that survives across multiple silicon generations. SCG scope spans architecture, design, software, operations, platforms, and productization. This role shapes system, platform, and data center features and behavior, and partners with teams across NVIDIA. What You'll Be Doing: The work here is rarely well-defined when it arrives. You will be given problems that appear to be performance gaps or power anomalies and encouraged to build a framework for solving them, not just tackle a single instance. Define the multi-generation roadmap for system-level power and performance features, grounded in prototyping, use-case analysis, and cost/benefit trade-offs across segments. You will decide what problems are worth solving and why. Own the architecture and integration strategy for HSIO power management, DVFS, P-states, and low-power features. Your decisions improve product performance, power, and reliability across product lines — not just the current program. Lead system-level boot and IST architecture defining how power and clock domains initialize, sequence, and recover across complex multi-IP systems where the interaction space is large and the failure modes matter. Drive power management strategy at data

NVIDIA is seeking a Senior Technical Program Manager to join the CSP Engagements team, focused on deep technical engagement with hyperscale cloud service providers for NVIDIA’s next‑generation datacenter systems such as Vera Rubin NVL72. This role is intended for experienced systems and embedded software leaders—including software engineering managers, technical leads, or senior architects—who have led datacenter server and platform software programs and can operate as a trusted technical partner to hyperscale CSP engineering teams. As a member of the CSP Engagements team, you will act as the primary technical engagement leader between NVIDIA’s system software organizations and CSP platform, system software, and AI teams, ensuring alignment, readiness, and successful large‑scale deployment of NVIDIA‑based datacenter solutions. What you will be doing: Lead deep technical engagements with hyperscale CSPs as the primary NVIDIA point of contact for system software, firmware, and platform readiness for NVIDIA datacenter products. Partner directly with CSP system software, firmware, and infrastructure engineering leaders to align on software architecture, bring‑up plans, deployment readiness, and production requirements for NVIDIA‑based server and rack‑scale platforms. Represent CSP technical priorities internally, advocating for customer requirements and tradeoffs across NVIDIA’s system software, firmware, hardware, silicon, and product teams are aligned to customer needs, timelines, and constraints. Own the end‑to‑end CSP engagement lifecycle, from early technical alignment and pre‑production readiness through large‑scale deployment, escalation management, and sustained production support. Drive bi‑directional technical communication: translating CSP system‑level requirements into actionable focus areas for NVIDIA engineering teams, while clearly communicating N

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about driving innovation for next-generation memory solutions powering AI/ML and high-performance computing systems. As a Director of HBM RTL Design and Integration, you will lead a team responsible for the design, integration, and delivery of next-generation HBM SoC logic die, with a strong focus on RTL development and IP integration. You will drive technical strategy and execution across multiple product generations, working closely with architecture, verification, physical design, firmware, and product engineering teams. Key Responsibilities Lead SoC RTL design and integration for HBM logic die, including subsystem partitioning, IP integration, and SoC-level design convergence. Drive translation of architectural and micro-architectural specifications into robust, high-quality RTL implementations across multiple teams. Oversee SoC integration aspects, including clocking, reset, power intent, configuration infrastructure, and system-level design correctness. Establish design methodologies and best practices to improve quality, reuse, and development efficiency across HBM programs. Partner with SoC Architecture, Verification, Physical Design, Firmware, and System teams to ensure successful end-to-end product execution. Work closely with Product Engineering, Test, Probe, Process Integration, Assembly, and Manufacturing to ensure robust, manufacturable HBM

About Team Our Robotics team is focused on unlocking general-purpose robotics and advancing toward AGI-level intelligence in dynamic, real-world environments. Working across the full model and systems stack, we integrate cutting-edge hardware and software to explore a broad range of robotic form factors. We strive to seamlessly blend high-level AI capabilities with the physical constraints of real-world systems to improve people’s lives. About the Role We are looking for a Technical Program Manager to own actuator development and integration from system goals through production readiness. The actuator program spans mechanical, electrical, firmware, harnessing, controls, test, reliability, manufacturing, and supply chain, and needs a TPM who can turn cross-functional decisions into clear scope, executable milestones, and timely decisions. In this role, you will help the team converge on the right technical plan, surface risks early, and deliver reliable actuator systems on schedule. This role is based in San Francisco, CA and requires in-person presence 4 days a week. In this role you will: Drive actuator programs end-to-end, aligning scope, milestones, interfaces, dependencies, and exit criteria across engineering teams. Drive scope lock and technical convergence for sprints, MVPs, and stretch goals while connecting component decisions to system performance. Coordinate actuator development across motors, gears, sensing, electronics, and firmware, and align the electrical and mechanical interfaces that connect actuators to the broader robot. Lead validation planning from early prototypes through engineering validation, reliability testing, and production readiness. Drive tradeoff decisions across cost, quality, performance, schedule, and lead time by collaborating cross-functionally and quantifying impact to meet program deliverables. Establish effective mechanisms for technical reviews, change control, design releases, decision tracking, and manufacturing readiness.

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first. We are hiring a Senior Manager to lead this team in the US and partner closely with teams globally. Your work will sit on the critical path of every NVIDIA silicon program, and the bar you set for system integration is the bar we ship to! The two hardest, highest-leverage problems in this seat: Find critical silicon issues earlier — often before software is production-ready. Left-shifting post-silicon coverage is the highest-value thing System Integration can do. Standing up wide-area testing as a repeatable capability is a core part of the role. Keep programs on milestone when upstream dependencies slip. Validation plans collide with reality every program! The team needs new strategies, not just contingency plans, to keep moving when software, firmware, or methodology slip. You will design and run those strategies. What you’ll be doing: Plan and execute post-silicon feature integration, PVT validation, and wide-area testing across NVIDIA’s GPU, SoC, and CPU programs. Build wide-area and in-system test as a repeatable capability that shifts post-silicon coverage left, so issues surface before we are production-ready. Lead resolution of the most complex system-level issues, RMAs, and HW/SW interaction problems with creative workarounds and focused lab experimentation. Deve