Firmware Engineer Bios Uefi Jobs

Engineer, Firmware Development (SSD) — MSB, Singapore. Apply via Workday.

Engineer, Firmware Development (SSD) — MSB, Singapore. Apply via Workday.

Staff/ Senior Engineer, Firmware Test (SSD) — MSB, Singapore. Apply via Workday.

Staff/ Senior Engineer, Firmware Test (SSD) — MSB, Singapore. Apply via Workday.

Senior/ Staff Engineer, Firmware Test (SSD) — MSB, Singapore. Apply via Workday.

Staff/ Senior Engineer, Firmware Test (SSD) — MSB, Singapore. Apply via Workday.

Engineer, Firmware Development (SSD) — MSB, Singapore. Apply via Workday.

Engineer, Firmware Design — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Senior/ Staff Engineer, Firmware Test (SSD) — MSB, Singapore. Apply via Workday.

Senior/ Staff Engineer, Firmware Test (SSD) — MSB, Singapore. Apply via Workday.

Staff Engineer, Embedded Security, Firmware Development (SSD) — MSB, Singapore. Apply via Workday.

Staff / Senior Security Engineer, Firmware Test, SSD — MSB, Singapore. Apply via Workday.

Principal / Staff Engineer, Embedded Security, Firmware Development (SSD) — MSB, Singapore. Apply via Workday.

About the Team The Release Engineer team is responsible for building and maintaining the systems that power software delivery—from CI/CD pipelines and artifact management to release automation and fleet telemetry. We ensure software across bootloaders, firmware, operating systems, and cloud services is built reproducibly, validated rigorously, and released safely at scale. About the Role As a Release Engineer, you’ll design, build, and operate release infrastructure that enables reliable, secure, and traceable software delivery across complex multi-component systems. You’ll partner closely with embedded, cloud, and QA teams to ensure that every build—from development to OTA deployment—is fast, verifiable, and production-ready. We’re looking for engineers who take pride in automation, build reproducibility, and system reliability—and who enjoy building the connective tissue that allows hardware and software to ship together seamlessly. This role is based in San Francisco, CA. We use a hybrid work model of four days in the office per week and offer relocation assistance to new employees. In this role, you will: Design and operate CI/CD pipelines for multi-component builds (bootloader, firmware, OS images, backend, companion apps) using hermetic toolchains. Define versioning and branching strategies; automate promotions, changelogs, and artifact retention. Integrate unit, integration, and hardware-in-the-loop (HIL) test results; quarantine flaky tests, auto-bisect failures, and block unsafe promotions. Build A/B OTA update flows with verity and health checks; run staged rollouts and canaries; implement safe rollback and roll-forward strategies. Implement code signing for binaries and firmware, generate SBOMs, run vulnerability scanning, and attach build attestations and provenance. Manage dashboards and alerts for build health, promotion latency, failure rates, and fleet update telemetry. You might thrive in this role if you: Have experience building and operating buil

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for a Rack Power Engineer with deep expertise in high-power conversion and distribution to design, qualify, and support power systems for AI supercomputers. You will own rack power solutions—including power shelves, AC/DC rectifiers, power supply units (PSUs), power management controllers (PMCs), and high-current distribution—from requirements and supplier development through deployment. You will also monitor fleet rack power health, lead debugging and root-cause investigations, and drive improvements into hardware, firmware, and qualification coverage. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own rack power architecture and requirements for high-power AI supercomputing systems, including power budgets, AC input interfaces, DC distribution, redundancy, efficiency, serviceability, and integration with data center infrastructure. Drive the design and supplier development of power shelves, rectifiers, PSUs, PMCs, busbars, connectors, and protection circuits. Review electrical designs and control behavior, and evaluate performance, cost, reliability, and availability trade-offs. Define and execute component, shelf, and rack qualification plans covering load transients, current sharing, hot-swap, startup and shutdown, redundancy failover, fault protection and recovery, thermal limits, and AC disturbances and ride-through