Nvidia Manager Jobs

We are now looking for a Senior Deep Learning Software Engineer, PyTorch. NVIDIA is hiring software engineers to design and build tools used by AI engineers across the world to design, develop, and deploy AI applications scalable across thousands of GPUs. This position will embed you in an ambitious and diverse team that influences all areas of NVIDIA's AI platform as well as directly contributes to PyTorch, a premiere deep learning framework. In this role you will work with multiple teams at NVIDIA across fields, as well as collaborate internationally with the PyTorch community to develop the best AI platform in the world. What you will be doing: Design and build PyTorch components that run efficiently on supercomputers with 1000s-100ks of GPUs. Collaborate with NVIDIA’s hardware and software teams to improve the overall GPU performance in PyTorch. Design, build and support production AI solutions used by enterprise customers and partners. Work with internal applied researchers to improve their AI tools. What we need to see: BS in Computer Science or Engineering (or equivalent experience). 3+ years professional experience in deep learning. Proficient with C++ programming. Strong understanding of systems software and interfaces. Demonstrated experience with Thread and Distributed Parallel Programming Demonstrated background developing large software projects. Strong verbal and written communication skills Ways to stand out from the crowd: Contributions and participation in the open source community. Familiarity with deep learning compilers. Familiarity with deep learning modeling trends. Background with CUDA Programming as well as Python.

NVIDIA’s Executive Briefing Center (EBC) Solutions Architect (SA) team is looking for a highly hands-on Solutions Architect with exemplary communication skills. The role involves developing, demonstrating (in the NVIDIA EBC), and packaging agentic AI systems. Partnering with account SAs you will co-develop proof of concepts (POC) and "uplift" their presentation quality to match the NVIDIA branding and messaging used with Executive meetings. This is a builder’s and presenter's role! You will spend time architecting and writing code. You will develop multi-agent systems, retrieval pipelines, and optimized inference stacks on NVIDIA’s full-stack accelerated computing platform. We want a creative, diligent, and curious engineer energized by agentic AI and ready to make significant change. If that’s you, join us! What you’ll be doing: Architect, build, and ship end-to-end Agentic AI applications for a variety of use cases—spanning multi-agent coordination, long-horizon reasoning, planning, and tool use. Act as Technical Advisor alongside fellow Subject Matter Experts (SME) in Executive Briefings. Creating and presenting demos that are used at Trade Shows or Customer Meetings. Partner with NVIDIA engineering, product, and sales teams to secure build wins, translate customer feedback into actionable product and roadmap insights, and scale global expertise through technical collateral, workshops, and developer communities. What we need to see: BS/MS/PhD in Computer Science, Electrical/Computer Engineering, Physics, Mathematics, AI/ML, or a related field (or equivalent experience) 2+ years as an ML/Software Engineer or Solutions Architect writing production-level code in Python and/or C/C++ in Linux environments. Validated experience building sophisticated agentic and multi-agent AI sy

NVIDIA Architecture Modeling group is looking for Architects, Functional Modeling Engineers, and Simulation experts to join various architecture efforts across GPU/ SOC Architecture teams. A key part of NVIDIA's strength is to innovate in parallel computing fields, delivering the highest performance in the world for high-performance computing. We are constantly looking for ways to improve our SoC and Systems architecture and maintain our leadership. In this position, you will be working with other world-class architects on modeling, analysis and validation of chip & system architectures and features that advance the state of art in performance and efficiency. What you'll be doing: Modeling and analysis of SoC & Systems algorithms and features, across datacenter, automotive, and client products Build and deliver platforms for SOC's that enable left shift for the SW teams aligned with project milestones Work closely with the SOC architects and guide modeling teams to deliver high-quality functional models that involve SOC+GPU use cases Collaborate with our EDA partners to align on customer-facing technologies Develop tests, test plans, and testing infrastructure for new architectures/features and code coverage analysis and reporting Ensure alignment between the various modeling teams at NVIDIA, GPU modeling teams, and modeling teams overseas What we need to see: Master’s or PhD in Computer Science, Electrical Engineering, Computer Engineering, or a related relevant field (or equivalent experience) with 5+ years of relevant work experience. Strong programming ability: C++, C along with a good understanding of build systems (CMAKE, make) , toolchains (GCC, MSVC) and libraries (STL, BOOST) Computer Architecture background with experience in modelling wit

NVIDIA’s Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first-principles thinking and engineering judgment at the highest level translate directly into product outcomes at scale. We are looking for a Principal Performance and Manufacturing Architect who has built the models, defined the specs, and seen them validated through silicon. You have owned the connection between design intent and manufacturing reality, not as a reviewer or a contributor, but as the person who set the methodology and proved it worked. You turn ambiguous physical phenomena into quantified, defensible margin terms. You do not wait for data to confirm your hypothesis; you design the experiment that gets it. You improve how the organization ships products after every program. The exceptional hire also uses AI deliberately — with proven workflow impact and the judgment to know where it compresses real work and where it introduces risk. What you'll be doing: Own the physics, from mechanism to margin. Build first-principles models connecting AVF, defect mechanisms, and DVFS transients to field FIT, system-level yield, and DPPM vs. coverage — calibrated per node and population shift — so every margin term in the V/F curve and P-state table is named, sourced, and defensible. Set the screen that resolves escapes. Specify ATE and SLT voltage, frequency, and timing conditions that capture worst-case transient VF windows — making it unambiguous whether a marginal defect or timing violation is detected or escapes at every manufacturing stage. Make the POR the authoritative source. Author the methodology document for each program and drive alignment across build, product definition, reliability, and test engineering — so every team is making decisions from the same model. Prove the model before produc

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are a world - class autonomous driving hardware and software development team. We have the best platform and have maintained a leading position in the field of artificial intelligence. Next, we will continue to deepen our efforts in the autonomous driving field and strive to bring sustained growth to our customers. We're looking for a Senior Software Triage Engineer with strong technical ability to deeply understand architectures and strong scripting experience to automate and Triage methodology, and the leadership to encourage our engineering team. As a key member of our automotive group, you'll be working on the real time challenges outstanding to the automotive industry and our automotive products. This is a key role to support AV software agile iteration & development for the release of clients, together working with the engineering teams, understanding the AV stack deeply and providing data-based judgement and delivering high-quality AV software to end customer. What you’ll be doing: Work with Product, Engineering, Model/SW Devs, In-car testing, Fleet teams on test request and triage planning, do live triage with accurate analysis and debugging steps, present top issues by end of day. Deep understand

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. As a Formal Verification Engineer at NVIDIA, you will verify the build and implementation of the industry's leading GPUs. In this position, your responsibilities will be to verify the micro-architecture using formal verification tools, define the verification scope, and ensure correctness. You will employ sophisticated formal techniques to acquire sufficiently bounded proofs while working with architects, designers, and pre- & post-silicon verification teams to accomplish your tasks. You will efficiently complete the formal verification effort for the entire project cycle, delivering high-quality results on schedule, and clearly conveying those results to the team. What you will be doing: Identify key behaviors for verification to write clear testplans for sophisticated designs. Implement testplans using the latest formal techniques, including the development of environment assumptions, assertions, and cover properties. Develop abstraction models to overcome complexity challenges and acquire full proofs, or bounded proofs with sufficient coverage. Drive formal tools to realize their best performance. Debug RTL to identify causes of failure scenarios. Contribute to flow and script development

The NVIDIA PerfTech team is looking for an outstanding Senior C++ Software Engineer to build the next generation of AI-powered developer tools. You will apply deep expertise in modern C++, systems architecture, performance, and debugging to extend our developer-tools ecosystem into the emerging world of agentic software. In this role, you will help develop Genie, NVIDIA’s company-wide AI knowledge and developer-productivity service. You will build production-quality C++ components and integrations while contributing to agentic workflows and retrieval systems that help engineers find information, understand complex systems, and work more effectively. What You’ll Be Doing: Architect and develop production-quality C++ components, APIs, and integrations for NVIDIA’s AI-powered developer-tools ecosystem. Build reliable, performance-sensitive systems connecting native C++ tools with Genie’s retrieval and agentic capabilities. Design maintainable interfaces between C++ applications and AI services exposed through Python, MCP, REST APIs, and structured tool calling. Contribute to agentic workflows, retrieval systems, ingestion pipelines, evaluation infrastructure, and enterprise integrations. Drive technical initiatives from early exploration through production deployment, working closely with multidisciplinary engineering teams. Mentor engineers and help establish best practices for production-quality AI-powered systems. What We Need to See: Bachelor’s or Master’s degree in Computer Science, Software Engineering, or a related field, or equivalent practical experience. 5+ years of professional experience developing complex production software in modern C++. Strong knowledge of software architecture, concurrency, debugging, performance optimization, and maintainable API design. Exper

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology and amazing people. Today, we're harnessing the boundless possibilities of AI to build the next era of computing. An era in which our GPU acts as the brain of computers, robots, and self-driving cars that can understand the world. Accomplishing unprecedented goals calls for imagination, inventiveness, and exceptional talent from around the world. As a NVIDIAN, you'll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Join our team and discover how you can build a lasting impact on the world. NVIDIA designs the silicon behind AI, accelerated computing, and graphics. Power and thermal architecture decisions sit behind every watt of performance and every degree of thermal headroom! We are the Silicon Co-Design Group (SCG). We are hiring a Principal Architect to scout the research and industry landscape, identify emerging system-level co-design ideas in power and thermal, and drive them across teams into product differentiation across NVIDIA's roadmap. This role shapes system, platform, and datacenter feature/behavior, and partners with teams across Nvidia. SCG scope spans across architecture, design, software, operations, platforms, and productization. What you'll be doing: Architect next-generation system, platform, and datacenter-level power and thermal co-design solutions. Scan internal research, academia, standards bodies, and silicon, memory, packaging, and platform partners for what is emerging. Build the product differentiation case for each candidate idea, performance, power, reliability, schedule, cost, and brainstorm what is worth pursuing. Lead end-to-end co-design from concept to product. Drive alignment across architecture, VLSI, softw

The DFP Engineer – Manufacturing role defines and implements the validation and screening of new silicon features within high‑volume manufacturing flows. You will translate product requirements into executable test methodologies, infrastructure, and detailed manufacturing test plans that ensure quality, yield, and efficiency at scale. This role sits at the intersection of multiple multi-functional teams to make manufacturing test an outstanding part of the overall codesign and DFP lifecycle. What you will be doing: Own end-to-end manufacturing test methodology across all test stages. Translate system specs and product POR into DFP requirements, test content, coverage, and flows. Define and maintain the DFP roadmap, including infrastructure and turning point planning. Partner multi-functionally to implement test content, debug hooks, and coverage improvements. Drive alignment on manufacturability, test time, binning strategies, and cost vs. coverage trade-offs. Embed testability requirements into design to enable robust screening and debug. Define data and analytics frameworks to support yield analysis and continuous improvement. Lead DFP documentation as the single source of truth and feed findings into future methodologies. What we need to see: MS in Electrical Engineering, Computer Engineering, or related field (or equivalent experience) 6&#43; years in silicon post‑silicon validation and/or high‑volume manufacturing test for complex SoCs, GPUs, CPUs, or similar. Hands‑on experience with test content bring‑up, limit setting, correlation to characterization, and yield/coverage optimization. Proficiency with scripting and data analysis (e.g., Python, MATLAB, R, SQL) for test data analytics, limit tuning, and yield/debug analysis. <

As one of the technology industry's most desirable employers, NVIDIA has been redefining accelerated computing, computer graphics and leading the Artificial Intelligence revolution. NVIDIA's innovation is fueled by its great technology—and amazing people. We are seeking a Senior Silicon and System Product Lead to influence, innovate and take our next generation products to the market. As part of the Silicon Solutions Team, we architect and deliver groundbreaking system solutions that integrate all aspects of the system from silicon design, software design to operations and final deployment in multiple market segments that NVIDIA serves. This position offers an unique opportunity to collaborate with multiple organizations in the company and grow your career in a high impact role. We need a passionate, hard-working and creative individual to lead the products all the way from market analysis to delivering the features on the final product. What you'll be doing: Drive product performance and power targets, trade-off features/configurations and provide innovative solutions to complex silicon and system level problems. Evaluate new market segments and use cases; translate market requirements to engineering problem statements and metrics. Innovate Performance, power, yield and quality optimizations and features for the world’s fastest power-shipping products in the GPU and SoC market segments spanning gaming, automotive, datacenter and DL/AI. Develop methodologies and requirements for multi-functional teams to drive silicon and system product features to production. Incorporate productization feedback to improve the next generation. Lead the team for feature requirements and schedule from architecture to silicon phase of projects. Work alongside system architects, designers, marketing teams, chip and board designers, software/firmware engineers, HW/S

The SCG Architecture team is hiring a Senior Power Integrity Co-Design Engineer to architect and deliver di/dt mitigation across silicon, package, board, and platform. This role bridges architecture, silicon, and platform — translating product noise targets into shipped specifications, and feeding silicon findings back into the next generation's build. Success in this role requires strong systems thinking and a willingness to accept ambiguity. It also requires the ability to apply AI as a force multiplier while maintaining rigorous engineering judgment. What you'll be doing: Architect voltage-noise mitigation across the full stack — silicon, package, board, platform — and own the codesign trade-offs between them. Co-design noise features with Speed, Power, Reliability, Circuit Design , Power-Arch, ASIC, and platform teams. You're the connective tissue across the codesign web. Work with other team members to define product-level voltage noise targets, drive them to closure, and sign them off at shipment. Build and take ownership of the Sim-to-Si correlation methodology for noise. You know when a model is lying and when silicon is. Model and prototype next-gen noise features — transient sense, droop response, mitigation IP, and codify them so every future program inherits them. Lead show-stopper noise bugs during bringup. The critical issues stop with you. Drive architecture-level codesign tradeoffs across V/F Power Noise Reliability Thermal (Noise-Variation) and (Noise-to-Closure) boundary work, where the highest-leverage innovation lives. What we need to see: BS / MS / PhD in EE, CE, or related (or equivalent experience). 5&#43; years in silicon power integrity, voltage noise, or PDN. Deep expertise in at least one of

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brain of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As a NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. NVIDIA Silicon Codesign Group is seeking a versatile engineer to join the HW bring-up methodology team. The SCG team is uniquely positioned to have an end-to-end view of the product development cycle - from early architecture definition, through bringup, to product release. What will you be doing: Led end-to-end planning and on-time execution of Nvidia's new chip bringup effort, from pre-silicon through production deployment. Coordinate multi-functional teams across Architecture, Build, Validation, DFT, SW, System, and Operations to drive shared bringup achievements. Improve cross-team communication, work, and handoffs. Develop and standardize methodologies, processes, and workflows for silicon bringup, creating reusable checklists and playbooks. Drive scheduling, equipment, and material logistics to support ambitious NPI and production schedules. Lead post-action reviews and convert learnings into concrete process improvements for future silicon and solution bringups. Contribute to post-silicon learnings that feed back into architecture, design, and pre-silicon

Build the infrastructure that keeps every NVIDIA chip aligned from first spec to final shipment. NVIDIA's Silicon Co-Design Group sits at the convergence of architecture, silicon, systems, and manufacturing. The System–Manufacturing Architecture (SMAC) team coordinates between system specifications and manufacturing test specifications from pre-silicon POR through production release across GPU, SoC, and CPU programs. When that alignment drifts, silicon faces the consequences: escapes, yield loss, and performance loss. We're hiring a Senior Manufacturing & System Co-Design Workflow Engineer to lead the methodology and infrastructure that maintains holistic, systematic alignment, at scale across the full portfolio. The strongest candidates in this role design the workflow before being asked to fix a program, and build the checks and automation that confirm alignment holds long after they've moved on to the next problem. What you’ll be doing: SMAC Workflow Methodology: Define manufacturing spec types, including schema and semantics, derived from system PORs and features. Own the methodology that governs how specification work gets structured, versioned, and validated across the program lifecycle. Production Python Pipelines & Automated Checks: Develop production-grade Python pipelines and automated checks that catch specification drift between system POR and manufacturing test programs ,ATE, SLT, BLT, L10&#43;, before silicon exposes the discrepancy. The goal is that misalignments surface in the workflow, not on the tester. E2E Program Integration & TPM Attestation: Wire SMAC work into the end-to-end program spine, milestones, gates, and artifacts, and define explicit TPM-driven attestation when checks lag. Alignment can't be assumed; it must be proven at every stage. Agent-Ready Tooling & CI Infrastructure: Integrate tooling into an agent-ready

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology and amazing people. Today, we're harnessing the boundless possibilities of AI to build the next era of computing. An era in which our GPU acts as the brain of computers, robots, and self-driving cars that can understand the world. Accomplishing unprecedented goals calls for imagination, inventiveness, and exceptional talent from around the world. As a NVIDIAN, you'll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Join our team and discover how you can build a lasting impact on the world. NVIDIA's Silicon Co-Design Group (SCG) leads the full product development lifecycle, from early architecture definition through silicon bringup to product release. The ArchDev team is the hub for silicon and system-level feature development, driving tradeoff analysis, system integration, and POR alignment across the entire organization. This is where ideas become chips, and chips become products that define the state of the art — and we're building that future with some of the most motivated engineers in the industry. We're looking for a Senior Memory Systems Engineer to own HBM and LPDDR integration in sophisticated SoCs. This role covers the full stack, including silicon, package, embedded software, testing, and product development. The engineer will resolve the toughest system-level memory challenges throughout the process, building solutions that hold up at scale. What you'll be doing: HBM & LPDDR System Integration and Bringup: Drive HBM and LPDDR system integration, bringup, characterization, and debug for next-generation SoCs — taking memory subsystems through the full arc from first silicon to production-ready at scale. Full-Stack Memory Closure: <s

Define the physical limits of what a chip can do, then break them! NVIDIA's Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first principles thinking translates directly into product outcomes at scale. As GPU power density and thermal limits approach physical boundaries, the gap between system architecture needs and manufacturable, testable capabilities widens with every generation, and this role exists to close it. You wouldn't be maintaining existing solutions, you'd be identifying where physical constraints will erode NVIDIA's competitive edge before anyone else sees it coming, then building the cross-domain responses that ensure the next generation leapfrogs those limits entirely. The problems here don't have known answers yet: Every generation of NVIDIA silicon pushes closer to the limits of physics. The Co-Design Architect role isn't about optimizing within known bounds; it's about redrawing those bounds entirely. If you want your work to shape what's physically possible in the world's most demanding computing products, this is where that work happens. What you'll be doing: Power, Thermal & Packaging Limits Analysis: Gather and analyze the hard constraints of packaging, power delivery, and thermal dissipation against roadmap demands, predicting when those constraints will reduce competitiveness and acting before they do. Cross-Domain Solution Development: Develop solutions that span silicon features, packaging innovation, firmware and hardware co-design, and DFX updates, ensuring future products are not only performant but testable to the highest quality and reliability standards. Packaging Technology Evaluation: Assess emerging packaging technologies for their voltage/frequency, noise, reliability, and testability implications, determining which are worth adopting an