Packaging Module Development Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Package Pathfinding Architect We are the team defining the future of packaging of complex memory systems! Our Package pathfinding and Architecture organization sits at the intersection of silicon, packaging, systems, and customer needs—turning complex scaling challenges into technologies that power next‑generation platforms, through cutting edge packaging technologies. If you enjoy working on problems with real industry impact, look no further. This is a technical pathfinding role driving forward-looking packaging technology for next generation memory systems from datacenter to edge-AI. You will leverage understanding of end‑to‑end memory system architectures, to guide long‑term package technology direction, and partner with customers, to build innovative ideas into scalable products. You will interface between package process technology, materials, electrical, thermo-mechanical and system performance areas to guide the package strategic roadmaps for Micron. Main Responsibilities: Define next‑generation package pathfinding and system architectures optimizing for speed performance, system bandwidth, power, capacity, thermal, mechanical and electrical performance. Lead cross‑stack co‑optimization across silicon, package, board, and system with package ce

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. An Operations Improvement Engineer is a key member of the Operations Improvement (OI) Team. This role is responsible for driving performance optimization across PWF, Assembly (HBM, advanced packaging) and T est Operations by identifying improvement opportunities in output, cycle time, cost, and efficiency. It involves applying industrial engineering principles to enhance core manufacturing functions such as line management, production planning, scheduling and dispatching. Additionally, the role supports factory automation initiatives by exploring and implementing innovative solutions that streamline processes and reduce variability. Key Responsibilities: Identify and analyze optimization opportunities within PWF, Assembly (HBM, advanced packaging) and Test

Job Details: Job Description: As the world's largest chip manufacturer, and a global leader in innovation and new technology, Intel strives to make every facet of semiconductor manufacturing state-of-the-art - from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth. We're constantly working on making a more connected and intelligent future, and we need your help. Change tomorrow. Start today. What we offer: We foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results. We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth. What we do: Join the Logic Technology Development (LTD) organization, a powerhouse of process technology innovation driving Intel's IDM 2.0 strategy to exceed the aspirations of our global customers. We are seeking a visionary Principal Engineer to lead the charge in Intel's foundry revolution, serving as a strategic technical architect and executive partner in guiding our most critical customers through the entire product development lifecycle. In this leadership capacity, you will orchestrate multidisciplinary strategies spanning device engineering, product integration, and yield analysis to steer customers from critical design tape-out and pre-silicon evaluation through to NPI silicon qualification. Furthermore, you will define t

About the team The Pricing & Monetization team is responsible for how OpenAI products create and capture value. We partner closely with GTM, Finance, and Product to design pricing models, packaging, and commercial strategies that support adoption, growth, and long-term scaling of the business. To thrive in this team, you need to be a proactive problem-solver who excels at bringing structure to ambiguous challenges. Our work demands strategic thinking, cross-functional collaboration, and precision in execution. Team members succeed when they are analytical, detail-oriented, skilled at balancing multiple priorities, and passionate about driving high-stakes projects forward to deliver meaningful results. About the role We are looking for a Pricing Strategist to shape the pricing frameworks, commercial policies, and decision principles that govern our most consequential commercial decisions. This role works closely with senior leaders across GTM and Finance to define our overall pricing strategy for our sales managed segment as well as the key pricing guardrails and commercial pricing framework we enable to help our sellers and customers move fast and land mutually beneficial commercial agreements at scale. The ideal candidate is comfortable developing durable monetization frameworks and commercial policies, analyzing tradeoffs, and supporting high-impact decisions. They bring structure to ambiguity, communicate tradeoffs crisply, and know when an exception reveals a one-off need versus a broader opportunity to improve our commercial model. This role will report to the Head of Go-to-Market Pricing. In this role, you will Develop frameworks and strategies that guide commercial pricing decisions. Design commercial constructs—including commitments, incentives, and risk-sharing approaches—that address customer needs while supporting healthy unit economics and long-term growth. Build and evolve discounting frameworks, guardrails, and approval principles that improve pric

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Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description: A senior advanced assembly technology development engineer is responsible for introducing new technology to enable next generation packaging. This position engaged latest stacking/flip chip technology, advance packaging material and work on new process set up, process/ packaging characterization and process transfer from TD phase to high volume production to meet development milestone. This position required high motivation and operation skill to build DOE sample and fulfill customer requirement sample as well as cooperate with Material engineer, Bumping, PI, NPI, quality and manufacturing team to ensure process transfer successfully. Responsibilities Explore new technology on semiconductor industry such as flip chip, TCB and hybrid bonding process equipment and packaging material. Provide plan and resource requirement to enable new technology. Set up DOE plan and execute. Build sample and perform data analysis skill. Lead efficiency trouble shooting skill to improve process. Prepare documentation for process transfer from TD to HVM Review process stability by FDC, SPC and test result. Self-motivated and capable of working independently, proactively identifying opportunities and driving projects with minimal direction. <span

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Advanced Packaging Technology Development (APTD) department at Micron Technology is at the forefront of innovation, driving the advancement of memory and storage Interconnects and Packaging solutions that transform how the world uses information. Micron is dedicated to developing innovative processes and technologies that enable the creation of next-generation semiconductor products which drive the AI revolution. By collaborating closely with our global R&D, equipment and materials suppliers, and manufacturing teams, we ensure the efficient development, transfer and implementation of new technology nodes, maintaining Micron's leadership in the industry. As a Realtime Defect Analysis (RDA) Technology Development Engineer in APTD, you will learn how to use pioneering defect detection equipment and processes to solve issues and drive improvement. The goal of this position is to accelerate cycles of learning and technology transfer in Technology Development (TD). We're seeking an engineer who is passionate about creative problem solving and finding innovative solutions. This position will provide the opportunity for you to collaborate with engineers in process integration, process development, data science, and yield analysis within and outside of TD. Your ideas will impact the team globally! We need someone who will investigate process anomalies through root-cause analysis, data manipulation, and correlations. You will be expected to support experimentation, data analysis, baseline health metrics, and systema

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We define ESD and latch-up architecture for next-generation HBM products across advanced nodes and 3D integration. Our team works across device, circuit, and packaging domains to solve reliability challenges that directly impact product quality. We take on complex problems and turn them into scalable solutions that enable high-performance memory! As an SMTS/DMTS HBM ESD/Latch-Up Architect, you will define protection strategies across base die, DRAM stacks, and interconnects. This role shapes product reliability from early architecture through silicon validation. You will work across teams and influence technical direction while solving system-level ESD challenges. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define end-to-end ESD and latch-up architecture across base die, DRAM die, and interconnects Develop protection strategies for high-speed I/O, TSV interfaces, and advanced packaging Establish ESD/LUP standards, rule decks, and signoff criteria Drive correlation between d

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As part of APTD SG Technology Development Process Integrator, you will be responsible for developing advanced packaging process solution and ensure New Process, New Equipment, New Material and Path finding activities success for all adv pkg products in Micron. To lead new Technode process readiness and improving the yield, quality and reliability with process characterization and optimization and new materials, machines & technologies introduction. You will need to have understanding of Frontend Process, packaging requirements, chip package interaction, equipment understanding and process technology in the industry. The ability to enable best technology for New Technode with packaging requirements. You will also be required to drive & collaborate with cross functional teams to resolve process related problems. Ensure smooth transition from new process development, 1st qualification success to small volume production launch Development and Qualification of new packaging process, material, equipment and technology solutions to meet new Technode requirements and schedule Perform CPI NUDD, process TRA, risk mitigation execution and process recipe readiness prior Silicon arrives and ensure 1st pass rate. Qualify new process/technology/equipment/materials Technical capability Identify path finding opportunities for Micron's technology leadership with BIC time to market, continuou

The Role We are seeking a highly skilled and hands-on SoC Floorplan Lead to own the physical foundation of our next-generation AI and Data Center SoCs. In this critical role, you will be the bridge between architecture, logic design, and physical design. You will work hand-in-hand with Chip Architects and RTL Leads to influence micro-architecture and ensure the physical implementation achieves best-in-class Power, Performance, and Area (PPA). If you love solving complex spatial puzzles on advanced technology nodes, integrating sensitive analog components, and driving execution in a high-energy start-up environment, this is the role for you. Key Responsibilities Top-Level Floorplanning: Own the SoC-level floorplan from concept to tape-out for high-performance, large-scale AI/Data Center chips on advanced process nodes (e.g., 5nm, 3nm or below). Architecture & RTL Collaboration: Partner closely with Architecture and RTL teams to provide early physical feasibility feedback. Drive block partitioning, shape optimization, and data-flow planning to achieve the absolute best PPA. Bump & Package Co-Design: Lead bump planning and IO ring definition. Work with packaging teams on flip-chip/advanced packaging constraints, ensuring optimal signal escape and power delivery. Custom & Analog Routing: Manage the placement and custom routing strategies for critical Analog/Mixed-Signal (AMS) IPs, high-speed SerDes (PCIe, Ethernet, Memory interfaces), PLLs, and sensitive clock distributions. Power Delivery Network (PDN): Design and analyze the top-level power grid, ensuring robust power delivery for high-current AI workloads while minimizing IR drop. Pin Assignment & Feedthroughs: Manage macro placement, block-level pin assignments, and top-level feedthrough planning to optimize global timing and routing congestion. Methodology Development: Build and maintain scalable Floorplanning workflows and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing coll

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Technology Development (TD) department at Micron Technology leads innovation. It drives the advancement of data retention and storage systems that change how the world uses information. The team develops next-generation semiconductor processes and technologies and works closely with global R&D and manufacturing teams to bring innovative solutions from concept to production. Join a collaborative environment where you will help shape the future of semiconductor technology while working alongside experienced engineers and technical leaders. Position Overview As a Process Integration Engineer in Advanced Packaging Technology Development (APTD), your role includes developing advanced packaging approaches and linking technologies. You will contribute to their integration in future semiconductor products. Working in a highly collaborative R&D environment, you will support process development, technology evaluation, and qualification activities while gaining hands-on experience with modern semiconductor technologies. This role provides an excellent opportunity for engineers who are passionate about innovation, problem-solving, and continuous learning. Responsibilities Support the development, characterization, and integration of groundbreaking packaging and interconnect solutions for next-generation semiconductor products. Collaborate with multi-functional engineering teams to analyze process data, solve technical challenges, and improve technology performance. Participate in e

Silicon Physical Design Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, fo

About the Team The Pricing & Monetization team is responsible for how our products create and capture value. We partner closely with Product, GTM, and Finance to design pricing models, packaging, and commercial strategies that support adoption, growth, and long-term scaling of the business. To thrive on this team, you need to be a proactive problem-solver who excels at bringing structure to ambiguous challenges. Our work demands strategic thinking, cross-functional collaboration, and precision in execution. Team members succeed when they are analytical, detail-oriented, skilled at balancing multiple priorities, and passionate about driving high-stakes projects forward to deliver meaningful results. About the Role We are looking for a Pricing Strategist with hands-on consumer pricing experience to shape how we price, package, and monetize our products across our consumer offerings. You’ll work closely with senior leaders across Product, GTM, and Finance to define pricing approaches, improve commercial decision-making, and bring more rigor to how we monetize our offerings. You should be comfortable building monetization frameworks and commercial policies, analyzing tradeoffs, supporting and driving high-impact decision-making. You should also care deeply about the customer perspective and believe that strong pricing reflects a real understanding of customer value, needs, and friction points in order to build pricing that is clear, fair, and aligned with how customers experience our products. This role will report to the Head of Product Pricing for Chat & Codex. What you’ll do Develop pricing and packaging strategy across subscription tiers, usage limits and entitlements, credits and overages, and emerging monetization models, balancing customer value, growth, and unit economics. Develop innovative commercial constructs to better serve our customers. Partner with Product, GTM, and Finance leaders to ensure pricing aligns with product value, the roadmap, commerc

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Description Position Summary As an IoT Engineer, Engineer based in Singapore, you will design, build, and deploy Industrial IoT (IIoT) and machine vision solutions to support advanced packaging technology development and factory enablement. You will implement hands-on engineering work from proof-of-concept through deployment and sustainment, contributing to scalable and secure solutions that improve quality, productivity, and early risk detection. You will collaborate cross-functionally to translate manufacturing needs into measurable signals, robust data pipelines, and actionable insights, while operating with a strong safety mentality and a bias for practical, reliable delivery. Key Responsibilities Develop and deploy IIoT solutions end-to-end: sensing strategy, edge compute, connectivity, data ingestion/storage, monitoring, and sustainment (including data quality and traceability). Build machine vision solutions: support hardware selection (cameras/optics/lighting), image acquisition strategy, algorithm development, performance validation, and deployment readiness. Work with process, equipment, automation, quality, and IT/data platfor