Senior Cpu Performance Architect Jobs

Senior CPU Performance Architect — 5 Locations. Apply via Workday.

Job Details: Job Description: Do Something Wonderful At Intel, we put silicon at the center of the world’s most meaningful innovations. From personal computing and AI to cloud-scale data centers and edge platforms, our processors power technologies that touch billions of lives. If you’re passionate about building world-class silicon at massive scale, we want to build the future with you. The Team You’ll join Intel’s All Cores Engineering (ACE) organization, the team responsible for designing and delivering Intel’s industry‑leading CPU cores. Within ACE, the Atom group focuses on high‑efficiency, performance‑per‑watt optimized cores that enable everything from client platforms to emerging edge and scalable solutions. This is a hands‑on senior engineering role with direct impact on next‑generation CPU silicon. What You’ll Do As a Senior CPU Design Verification Engineer you will play a critical role in ensuring architectural correctness, functional robustness, and power‑efficient performance of Intel’s Atom CPU designs before first silicon. Key responsibilities include but not limited to the following: Lead pre‑silicon functional verification of complex CPU and SoC logic to ensure full compliance with architectural and microarchitectural specifications. Develop and execute verification plans, testbenches, and SystemVerilog/UVM environments, ensuring comprehensive functional and coverage closure. Define, run, and analyze system‑level simulations to uncover functional, performance, power, and corner‑case issues. Debug and root‑cause complex RTL, microarchitecture, and integration issues; drive issues to resolution with design teams. Collaborate cross‑functionally with CPU architects, RTL de

At Snowflake, we are powering the era of the agentic enterprise. To usher in this new era, we seek AI-native thinkers across every function who are energized by the opportunity to reinvent how they work. You don’t just use tools; you possess an innate curiosity, treating AI as a high-trust collaborator that is core to how you solve problems and accelerate your impact. We look for low-ego individuals who thrive in dynamic and fast-moving environments and move with an experimental mindset — who rapidly test emerging capabilities to discover simpler, more powerful ways to deliver results. At Snowflake, your role isn't just to execute a function, but to help redefine the future of how work gets done. Snowflake’s cloud spend is in billions of dollars per year. Hence, it is critical for us to govern and optimize our cloud spend, both for margins and long-term competitive advantage. Cloud Efficiency team’s charter is to build scalable products that enable governance, monitoring and optimization of cloud spend. Think of this as Observability for cloud costs and efficiency. The team’s vision is to “Transform cloud spend into a competitive advantage by empowering teams to continuously optimize the per-unit cost.” In order to improve the overall cloud efficiency (i.e. cost per unit), it is critical to build monitoring products that collate costs with other factors such as utilization, attribution, hardware performance and architecture. Hence, there is an opportunity to build a unified, self-serve cloud efficiency product across Snowflake, that delivers actionable, real-time efficiency datasets through streamlined user experiences. This will enable thousands of engineers at Snowflake and will elevate cloud efficiency at Snowflake for long-term success. When developing these solutions, we think about the problem end-to-end: how do we collect data from different stacks (e.g. costs from AWS, GCP, Azure and CPU, Memory, Utilization) across Snowflake reliably, how do we store it eff

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We're looking for an Engineering Program Manager — or a technical engineer ready to move into program management — to help drive execution on our RISC-V CPU team. You'll work across architecture, design, verification, physical design, and DFT to keep a high-performance CPU program moving from spec through tapeout and post-silicon debug. Partnering with a senior program lead and engineering managers, you'll own schedules, track milestones, surface risks early, and keep cross-functional teams aligned. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experience in CPU, SoC, or silicon development — as an engineer, technical lead, or program manager. Comfortable working with cross-functional engineering teams and translating technical detail into clear status, dependencies, and trade-offs. Organized and proactive; you chase down open items rather than waiting for them to resolve. A clear communicator who can hold your own in engineering discussions and write updates leadership can act on. What We Need Support the full CPU development cycle — spec, design, verification, DFT, ta

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a highly technical Senior Staff/Principal Engineer to lead the porting and enablement of critical AI workloads. You will be a primary driver in migrating compute workloads to RISC-V architectures, ensuring our hardware is optimized for real-world application performance. The ideal candidate has a strong background in DevOps, workload porting, or application enablement . While this is an individual contributor role at its core, you will have the opportunity to grow and lead a small, specialized team over time as our workload migration efforts scale. This role is remote, based in the United States or Australia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A Technical Catalyst: You thrive on the challenge of driving AI hardware porting to RISC-V and making complex software stacks run efficiently on new hardware. Systems Expert: You possess deep knowledge of system software, compilers, or low-level OS internals. You are an expert in ARM or x86 environments and are ready to apply those skills to the RISC-V frontier. A Project Driver: You have the technical authority to lead the implementation of a compute migration to RISC-V through

NVIDIA is seeking a world-class computer architect to contribute to the development of future high-performance computing systems, with a focus on enhancing the power-constrained performance of the hardware. Ideal candidates will have a strong track record of understanding and analyzing memory systems architecture to improve performance per watt (perf/W) and performance per millimeter (perf/mm). A broad perspective across the field of computer architecture and depth in the area of power, performance, and area (PPA) analysis is highly desirable. NVIDIA has pioneered programmable GPUs and the CUDA language and is a world leader in high-performance computing technology, with aggressive plans for future processors. This position offers the opportunity to have a real impact in a fast-moving, technology-focused company. What you will be doing: Develop innovative high-performance processor and system architectures, focusing on the memory system and energy efficiency. Develop architecture and micro-architecture features to improve the state-of-the-art in GPU memory systems, optimizing along the axes of perf/W, perf/mm, and perf/$. Develop and enhance architecture prototype models for power and noise analysis. Participate in performance and power simulation of features to analyze, define, and improve energy per byte. Analyze benchmarks, application workloads, and performance/power simulation and emulation results to identify areas for architecture optimizations. Debug power, performance, and functional issues with high-level models, RTL simulation and emulation, silicon, and systems. Collaborate with outside partners on system infrastructure. What we want to see: 10+ yrs of experience in CPU/GPU architecture, memory systems design with a focus on energy efficiency in the system. Bachelor

NVIDIA is leading company of AI computing. At NVIDIA, our employees are passionate about AI, HPC , VISUAL, GAMING. Our SA team is more focusing to bring NVIDIA new technology into difference industries. We help to design the architecture of AI computing platform, analysis the AI and HPC applications to deliver our value to customers, focusing on defining and solving computational challenges in LLM inference and training acceleration, as well as network communication and data transfer optimization. What You'll Be Doing: Contribute to the development of open-source inference frameworks such as SGLang and vLLM, including feature and operator development, performance optimization, and model support, in collaboration with the community. Develop and optimize KV cache offloading frameworks for LLM workloads, supporting multi-level cache offloading and reuse across CPU, SSD, and remote storage to improve inference efficiency. (Team project: FlexKV) Drive R&D on compute performance in distributed training, and explore methods and technologies for performance optimization. Study computational challenges in machine learning systems, identify common needs and bottlenecks, and build example code, acceleration libraries, or frameworks accordingly. What We Need to See: Over 5 years working experience in the technology industry, with master’s degree or above in computer science, mathematics, electrical engineering, automation, or related fields. Strong interest in accelerated computing, parallel computing, and heterogeneous computing, with the motivation to explore these areas in depth. Solid programming skills, with a good understanding of data structures and computer systems fundamentals. Strong learning agil

Join our multidisciplinary team and help build and improve GPU and CPU accelerated data processing software libraries. Projects like DALI or nvImageCodec are used in all kinds of processing workflows and support NVIDIA's vision and growth. Starting from powering AI, data analytics, image processing, computer vision, and scientific simulations for leading commercial and academic organizations worldwide. In this role, you will design, develop, and optimize pioneering algorithms. Ideal candidates will have experience with accelerated computing and a passion for advancing the state-of-the-art in various computing domains. If this sounds exciting, we would love to meet you! What you’ll be doing: Developing scalable library software using modern tools and languages for various numerical method. Performance tuning, optimization, and benchmarking of algorithms on various architectures. Working closely with leadership team and other internal and external partners to understand feature and performance requirements and contribute to the technical roadmaps of libraries. Providing technical leadership and guidance to library engineers working with you. Find opportunities to improve user experience and library performance. What we need to see: PhD or MSc’s degree in Computational Science, Computer Science, Applied Math, or related science or engineering field of study is preferred (or equivalent experience). 5+ years experience developing, debugging, and optimizing high-performance parallel numerical applications on modern computing platforms, with GPU acceleration using CUDA. C/C++ programming and software development skills. Proven experience in leading and completing software development projects. Strong collaboration, communicati

Build the infrastructure that keeps every NVIDIA chip aligned from first spec to final shipment. NVIDIA's Silicon Co-Design Group sits at the convergence of architecture, silicon, systems, and manufacturing. The System–Manufacturing Architecture (SMAC) team coordinates between system specifications and manufacturing test specifications from pre-silicon POR through production release across GPU, SoC, and CPU programs. When that alignment drifts, silicon faces the consequences: escapes, yield loss, and performance loss. We're hiring a Senior Manufacturing & System Co-Design Workflow Engineer to lead the methodology and infrastructure that maintains holistic, systematic alignment, at scale across the full portfolio. The strongest candidates in this role design the workflow before being asked to fix a program, and build the checks and automation that confirm alignment holds long after they've moved on to the next problem. What you’ll be doing: SMAC Workflow Methodology: Define manufacturing spec types, including schema and semantics, derived from system PORs and features. Own the methodology that governs how specification work gets structured, versioned, and validated across the program lifecycle. Production Python Pipelines & Automated Checks: Develop production-grade Python pipelines and automated checks that catch specification drift between system POR and manufacturing test programs ,ATE, SLT, BLT, L10+, before silicon exposes the discrepancy. The goal is that misalignments surface in the workflow, not on the tester. E2E Program Integration & TPM Attestation: Wire SMAC work into the end-to-end program spine, milestones, gates, and artifacts, and define explicit TPM-driven attestation when checks lag. Alignment can't be assumed; it must be proven at every stage. Agent-Ready Tooling & CI Infrastructure: Integrate tooling into an agent-ready

Job Details: Job Description: As a Senior Power and Performance (PnP) Engineer, you will be responsible for PnP product execution focused on measurements, analysis, and projections/estimates of Intel's unlaunched notebook and desktop products. Based on your technical knowledge of both Intel and the competition, you will help influence OEM customers, internal marketing teams, internal engineering teams, debug Intel silicon/platform on PnP issues, and be an integral part for Intel product launches. Core responsibilities to include following: Measure, analyze, and debug workloads to call out any power and/or performance gaps and close with internal engineering teams/architects Measure and analyze SoC/CPU and platform power on a rail by rail basis and debug any issues/gaps Align with other internal engineering teams and architects to ensure there is consensus on power and performance projections/estimates/measurements for both internal and external communication Guide, educate, and influence internal engineering teams, field account teams, and marketing teams on power and performance positioning of Intel products Create power and performance estimates on upcoming Intel products based on workloads to aid marketing decisions and help set internal KPI targets Own the publication of the Power Performance Guide (PPG) collateral to help guide OEM customers Bring up full test platform to enable both power and performance measurements including setup, calibration, and measurements. Qualifications: You mus

We are seeking a qualified Senior Software Tools Development Engineer to join our GPU SWQA team. The successful candidate will have strong experience applying AI technologies to automate test cases and a deep understanding of Windows operating systems. Extensive knowledge of GPU, CPU, SoC, x86, and ARM architectures is required, along with expertise in PC I/O architecture and common bus interfaces such as PCIe, USB, and SATA. Familiarity with specifications for general PC architecture components is a plus. What you’ll be doing: Design and implement automated tests incorporating AI technologies for NVIDIA's device driver software and SDKs on windows platforms. Build tools/utility/framework in Python, C# or equivalent which would help automate and optimize the testing workflows in GPU domain. Develop and carry out automated and manual tests, analyze results, identify and report defects. Rigorously drive test automation initiative. Build innovative ways to automate and expand our software testing. Expose defects and constraints; Isolate and debug the issue(s) and find the root cause; Contribute to the solution and drive to closure. Measure code coverage for the software under test, analyze and drive code coverage enhancements. Develop applications and tools that accelerate development and test workflows and write fast, effective, maintainable, reliable and well documented code. Generate and test compatibility across a range of products and interfaces and validate different key software applications across a test matrix designed to test both breadth and depth. Provide peer code reviews including feedback on performance, scalability and correctness. Report test coverage and Go/No-Go status for deliverables, escalate critical issues, and drive them to closure. Participate in root cause analysis and corrective actions to continuo

Here at Appian, our values of Intensity and Excellence define who we are. We set high standards and live up to them, ensuring that everything we do is done with care and quality. We approach every challenge with ambition and commitment, holding ourselves and each other accountable to achieve the best results. When you join Appian, you’ll be part of a passionate team dedicated to accomplishing hard things, together. Senior Consultant Location: Chennai, India | Work Model: In Office Appian Customer Success is obsessed with delivering exceptional customer outcomes and driving mission-critical business impact. Grounded in our core values of Excellence and Intensity, we act as elite technical advisors to our commercial clients. By joining this high-performance team, you will champion a culture of candid communication and excellence while accelerating global adoption of our AI-Powered Process Automation platform. What You’ll Do Implement Scalable Platform Architecture: Build and maintain standards and tools to ensure high performance and resilience with a focus on reusability, schema design, data modeling , query performance, and responsive UX/UI best practices. Engineered Integrations: Perform hands-on design, code implementation, and unit testing using SQL views , stored procedures , and high-concurrency REST/SOAP web services/APIs . System-Level Troubleshooting: Rapidly diagnose performance bottlenecks, memory usage, CPU constraints, and network latency spikes across the web application stack. Performance Profiling & Analysis: Analyze database execution plans, system logs, and Locust load test outputs to isolate and resolve root-cause performance bottlenecks. Technical Quality & Enablement: Ensure continuous integration and delivery alignment by applying strong DevSecOps practices, robust automated testing, and clean coding standards. Required Qualifications Bachelor’s Degree in Computer Science, Engineering, Information Systems, or Mathematics. 8+ years of pro

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which the GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As a Developer Technology Engineer you will be at the forefront of innovation, working with leading industry partners and exciting OSS projects to accelerate RTX & DGX SoC performance for agentic use. This role offers an outstanding opportunity to collaborate with world-class talent and make a significant contribution to the next era of enterprise and consumer AI. What you'll be doing: Own key engagements with our fast-paced developer ecosystem partners, optimizing their applications to deliver outstanding end-to-end performance on RTX and DGX SoCs. Take ownership of performance optimization for compute-intensive CPU, AI, and 3D graphics workloads, working with domain experts to identify bottlenecks and implement effective solutions. Work across system software, GPU driver, architecture, and NVIDIA Research teams to influence next-generation, high-performance SoC platforms by bringing real-world workflows and actionable insights from partner and customer needs. Provide technical guidance and mentorship to junior engineers while contributing to an inclusive and high-performing team environment. What we need to see: BS or MS degree in Computer Science, Engineering, Mathematics or related degree (or equivalent experience) 5+ years of respective work experience as software developer Proficiency in C/C++, Python, software

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer who will contribute to the physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout. You will partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs. Along the way, you will build end-to-end ASIC expertise while learning from experienced engineers across the chip development process. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An engineer excited to work on high-performance designs for industry-leading AI/ML architectures. A collaborative problem solver who enjoys working with experienced engineers across ASIC disciplines. Grounded in logic design fundamentals and gate- and transistor-level implementation. Curious about how early architectural and RTL decisions shape physical implementation and final chip quality. What We Need A BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a relat

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a senior High Speed Interconnect / Signal Integrity Engineer to design and validate high-bandwidth links for large-scale AI systems. You will define, model, and qualify interconnect solutions across copper and optical technologies for next-generation AI inference and training clusters. This role is on-site in Santa Clara, CA, Austin, TX, or Toronto, Canada. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting Who You Are An experienced electrical engineer with a Bachelor’s or Master’s in Electrical Engineering. 5+ years working on high-speed communications (100G–1.6T), including signal integrity, channels, and links. Comfortable building and owning link and channel budgets and making clear tradeoffs between reach, loss, BER, and margin. Hands-on with SI tools and lab equipment such as Keysight ADS, VNAs, TDRs, BERTs, and protocol analyzers. Familiar with cable specification and testing, as well as accelerated life testing, mating life, and failure analysis. Able to collaborate across hardware, systems, and manufacturing teams; manufacturing/DFM/DTM experience is a plus. What We Need Define and specify high-speed interconnect architectures