Senior Power Integrity Co Design Engineer Jobs

The SCG Architecture team is hiring a Senior Power Integrity Co-Design Engineer to architect and deliver di/dt mitigation across silicon, package, board, and platform. This role bridges architecture, silicon, and platform — translating product noise targets into shipped specifications, and feeding silicon findings back into the next generation's build. Success in this role requires strong systems thinking and a willingness to accept ambiguity. It also requires the ability to apply AI as a force multiplier while maintaining rigorous engineering judgment. What you'll be doing: Architect voltage-noise mitigation across the full stack — silicon, package, board, platform — and own the codesign trade-offs between them. Co-design noise features with Speed, Power, Reliability, Circuit Design , Power-Arch, ASIC, and platform teams. You're the connective tissue across the codesign web. Work with other team members to define product-level voltage noise targets, drive them to closure, and sign them off at shipment. Build and take ownership of the Sim-to-Si correlation methodology for noise. You know when a model is lying and when silicon is. Model and prototype next-gen noise features — transient sense, droop response, mitigation IP, and codify them so every future program inherits them. Lead show-stopper noise bugs during bringup. The critical issues stop with you. Drive architecture-level codesign tradeoffs across V/F Power Noise Reliability Thermal (Noise-Variation) and (Noise-to-Closure) boundary work, where the highest-leverage innovation lives. What we need to see: BS / MS / PhD in EE, CE, or related (or equivalent experience). 5+ years in silicon power integrity, voltage noise, or PDN. Deep expertise in at least one of

Shape the Future with Dun & Bradstreet At Dun & Bradstreet, we believe data has the power to create a better tomorrow. As a global leader in business decisioning data and analytics, we help companies worldwide grow, manage risk, and innovate. For over 180 years, businesses have trusted us to turn uncertainty into opportunity. We’re a diverse, global team that values creativity, collaboration, and bold ideas. Are you ready to make an impact and help shape what’s next? Join us! Explore opportunities at dnb.com/careers. Sr. Data Cloud Engineer(s)(multiple positions) – Duties are using relational database systems, CI/CD pipeline, Kubernetes for application deployments, terraform IAC, Observability using Splunk, server-side GitHub REST API, & Snowflake, Spark, & Python to design, automate, implement & maintain data architecture patterns in AWS & GCP for data collection infrastructure & pipelines for multi-region cloud-based big data IaaS & PaaS solutions including performing requirements & document use technology analysis; coordinating data integration & ETL processes; supporting data security, integrity & cost controls; automating data processes utilizing Cloud Composer & develop SQL scripts for data modeling; performing end-to-end pipeline load performance testing; supporting technology upgrades through PostgreSQL & Cloud SQL cloud migrations; performing SQL & NoSQL database tuning & maintenance; providing guidance on data management & SQL optimization; & developing data warehousing management policies. Requires Bach degree in Comp Science, Comp Engineering, Information Technology (IT) or related field & 5 yrs exp in job duties as stated. Position is with Dun & Bradstreet in Jacksonville, FL. Inquire and send resume through Dun & Bradstreet’s job board at https://jobs.lever.co/dnb. Position is under Sr. Data Cloud Engineer for Jacksonville, FL. #LI-DNI

NVIDIA's Silicon Co-design Group (SCG) sits at a rare intersection: we own the full product development lifecycle, from early architecture definition through silicon bringup to product release. Our ArchDev team is the hub for silicon and system-level feature development, driving tradeoff analysis, system integration, and POR alignment across the entire organization. If you want to see your work go from whiteboard to world-class silicon, this is where that happens. What You'll Be Doing: Architect and integrate system-level performance and power management features, controllers, and policies to optimize product efficiency across datacenter and client products . Build feature roadmaps to address low-power, low-noise, and performance-per-watt product needs through prototyping, use-case analysis, and cost/benefit trade-offs. Partner with architecture, ASIC, board/platform, software/firmware, and marketing teams to drive design decisions and debug complex issues. Track industry trends and market needs and translate them into forward-looking roadmaps that keep NVIDIA's products ahead of the curve. Lead debug efforts, develop workarounds, and support bringup , validation, manufacturing, and customer escalations. What We Need to See: <

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. NVIDIA’s Silicon Co-Design Group is hiring a Chip Lead to serve as the technical lead for one of our most consequential silicon programs! This is not project management, and it is not a senior IC role. You are the person the program partners with on its hardest technical questions — when the right answer is not obvious, and when leadership needs a single technical perspective to align on direction. You are accountable for the technical integrity of the chip end-to-end. You guide co-design feature integration, help resolve the toughest multi-functional bugs, and serve as the project-specific custodian of the qualification playbook. The program runs cleaner because you are on it! What you’ll be doing: You will partner across design, validation, software, and manufacturing to keep the program’s technical narrative clear and on track. Day to day, you will: Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs. Co-lead program-level feature integration from chip to system, surfacing inter-function dependencies and guiding them to resolution. Help resolve the program’s hardest multi-functional bugs by translating ambiguous, multi-team symptoms into root-cause closure on areas such as HBM, power and thermal, high-speed I/O, and packaging. Steward the qualification playbook. When the playbook does not fit a situation, guide the mitigations and capture the lessons as reusable methodology for other SSG programs. Shape the program’s technical narrative by surfacing key risks, trade

We believe that the way people interact with their finances will drastically improve in the next few years. We’re dedicated to empowering this transformation by building the tools and experiences that thousands of developers use to create their own products. Plaid powers the tools millions of people rely on to live a healthier financial life. We work with thousands of companies like Venmo, SoFi, several of the Fortune 500, and many of the largest banks to make it easy for people to connect their financial accounts to the apps and services they want to use. Plaid’s network covers 12,000 financial institutions across the US, Canada, UK and Europe. Founded in 2013, the company is headquartered in San Francisco with offices in New York, Washington D.C., London and Amsterdam. About The Team The Internal Controls team designs and oversees Plaid’s SOX compliance and internal control framework to ensure accurate financial reporting and operational integrity. We partner cross-functionally to support IPO readiness, build scalable audit foundations, and drive trust in Plaid’s financial systems and processes through strong controls, collaboration, and continuous improvement. Role Descriptioin As the Internal Controls Manager, you will design, implement, and lead Plaid’s SOX compliance and internal control programs. You will partner with cross-functional teams to build scalable, efficient controls that support IPO readiness and long-term compliance. You will manage external advisors, drive remediation efforts, and serve as a key liaison to auditors and senior leadership. Over time, you’ll build and lead a team, expand audit coverage, and continuously improve our control environment through automation and risk-based processes. Responsibilities Maintain and optimize Plaid’s SOX internal controls program to support IPO readiness. Partner with process and control owners to develop, document, and maintain effective, scalable internal controls across key functions. Manage and grow co-

Join us in building the future of finance. Our mission is to democratize finance for all. An estimated $124 trillion of assets will be inherited by younger generations in the next two decades. The largest transfer of wealth in human history. If you’re ready to be at the epicenter of this historic cultural and financial shift, keep reading. About the team + role We are building an elite team, applying frontier technologies to the world’s biggest financial problems. We’re looking for bold thinkers. Sharp problem-solvers. Builders who are wired to make an impact. Robinhood isn’t a place for complacency, it’s where ambitious people do the best work of their careers. We’re a high-performing, fast-moving team with ethics at the center of everything we do. Expectations are high, and so are the rewards. The Communications Compliance team ensures our parent company and affiliate entities maintain the highest standards of regulatory and brand integrity. We review, audit, approve, and advise on a wide range of public-facing retail communications, partnering closely with Marketing, Legal, Content, and Compliance teams. As a Communications Compliance Senior Specialist, you will review and advise on parent company and enterprise-level communications, including select third-party advertising content, and work with business compliance on multi-entity communications. You will provide guidance early in the creative process and support internal teams in meeting regulatory requirements and internal policies. This role plays a key part in ensuring communications align with FTC, SEC, FINRA, CFTC, FCA, and other applicable regulatory standards. You will also contribute to strengthening review processes and documentation practices that support consistent, high-quality compliance oversight. This role is based in our Menlo Park, CA, New York, NY, Washington, DC, or Denver, CO offices, with in-person attendance expected at least 3 days per week. At Robinhood, we believe in the power of

GitLab is the intelligent orchestration platform for DevSecOps. GitLab enables organizations to increase developer productivity, improve operational efficiency, reduce security and compliance risk, and accelerate digital transformation. More than 50 million registered users and more than 50% of the Fortune 100* trust GitLab to ship better, more secure software faster. The same principles built into our products are reflected in how our team works: we embrace AI as a core productivity multiplier, with all team members expected to incorporate AI into their daily workflows to drive efficiency, innovation, and impact. GitLab is where careers accelerate, innovation flourishes, and every voice is valued. Our high-performance culture is driven by our values and continuous knowledge exchange, enabling our team members to reach their full potential while collaborating with industry leaders to solve complex problems. Co-create the future with us as we build technology that transforms how the world develops software. * Fortune 500® is a registered trademark of Fortune Media IP Limited, used under license. Claim based on GitLab data. Fortune 100 refers to the top 20% ranked companies in the 2025 Fortune 500 list, published in June 2025. Fortune and Fortune Media IP Limited are not affiliated with, and do not endorse products or services of GitLab. An overview of this role As a Senior Backend Engineer on the Duo Chat team, focused on Chat Engine, you'll build the core AI capabilities behind GitLab Duo Chat, the natural-language and agentic interface to the GitLab DevSecOps platform. Much of your work will involve building flow components and agentic flows in the Flow Registry, the Python framework built on LangGraph within our Duo Workflow Service that powers agentic chat, and integrating them with the GitLab Rails monolith. You'll own complex backend features from start to finish across both services. You'll integrate large language models and orchestrate multi-agent flows

Design Methodology – Senior / Staff DRAM Power Integrity Engineer — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Sr Design Engineer, you will work on design, simulation, and validation of next ‑ generation High ‑ Bandwidth Memory (HBM) architectures and circuit blocks. HBM requires advanced DRAM design knowledge combined with deep understanding of 3D stacked architecture, TSV signaling, wide I/O interfaces, PHY timing, power integrity, and system co ‑ optimization with GPUs/accelerators. This role sits at the intersection of DRAM design and high ‑ performance computing, enabling future AI/ML, HPC, and advanced graphics products. In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction.

Our Purpose Mastercard powers economies and empowers people in 200&#43; countries and territories worldwide. Together with our customers, we’re helping build a sustainable economy where everyone can prosper. We support a wide range of digital payments choices, making transactions secure, simple, smart and accessible. Our technology and innovation, partnerships and networks combine to deliver a unique set of products and services that help people, businesses and governments realize their greatest potential. Title and Summary Senior Data Scientist-2 Overview Product Data & Analytics is a centralized global team that enables Mastercard product business units to make better data‑driven decisions. We build internal analytics partnerships that strengthen focus on business performance, portfolio and revenue optimization, initiative tracking, new product development, and go‑to‑market strategies. These capabilities are underpinned by our data platforms that enable insights to be delivered in a standardized, scalable, and cost‑efficient manner. Key Responsibilities Strategic Support • Design and implement value enablement frameworks that optimize pricing strategies, enhance pre-sales propositions, and ensure customer success. • Collaborate with global and regional teams to tailor solutions that meet regional business needs and align with Mastercard's objectives. • Provide data-driven insights and recommendations to optimize pricing, pre-sales strategies, and customer success outcomes. • Develop frameworks, project structures, and presentations to communicate key strategic initiatives. • Conduct data integrity checks and ensure quality and reliability in data used for analysis. • Translate complex business problems into analytical solutions that support strategic decision-making. Technical Leadersh

About Scale At Scale AI, our mission is to accelerate the development of AI applications. For 8 years, Scale has been the leading AI data foundry, helping fuel the most exciting advancements in AI, including: generative AI, defense applications, and autonomous vehicles. With our recent Series F round, we’re accelerating the abundance of frontier data to pave the road to Artificial General Intelligence (AGI), and building upon our prior model evaluation work with enterprise customers and governments, to deepen our capabilities and offerings for both public and private evaluations. About Data Engine Our Generative AI Data Engine powers the world’s most advanced LLMs and generative models through world-class RLHF (Reinforcement Learning with Human Feedback), human data generation, model evaluation, safety, and alignment. The data we are producing is some of the most important work for how humanity will interact with AI. Our Approach As part of the interview process, you’ll be considered for opportunities across several teams within the GenAI Engineering organization, based on your interests, expertise, and business needs. Potential team placements include Allocation, Growth, Frontier Data, Trust & Safety, Pay, Operator, or Tasking Experience. Together, these teams power Scale’s AI data operations - from building high-impact datasets that push the boundaries of LLM capabilities, to optimizing contributor onboarding and incentives, to safeguarding data integrity through advanced trust, safety, and security measures. They work at the intersection of ML, operations, and analytics to ensure we deliver the highest-quality data at scale. Responsibilities: Design, build, and maintain robust, scalable systems across the full stack, including front-end, back-end, and infrastructure layers Implement high-impact features using modern technologies such as TypeScript, React, Node.js, MongoDB, Elasticsearch, and Temporal Collaborate closely with internal operators (your use

We are now looking for a Senior SRAM Engineer within our Full Custom Memory (FCM) team! The FCM team designs specialized RAM implementations across NVIDIAs wide array of processing chips. Be it high speed, low power, multiport, we engage closely with processor architecture teams to build custom solutions across the entire NVIDIA silicon portfolio. Are you interested in designing circuits for the next generation of AI chips? Join a team of dedicated engineers developing the custom SRAM circuits that help power these chips. What you'll be doing: Design best-in-class SRAM circuits using state-of-the-art technology processes Optimize circuits for performance, area, and power Collaborate with mask designers to craft high quality and dense pitch-matched layout Verify functionality, electrical integrity, and robustness Improve/develop flows and methodologies to streamline design automation, data collection, and analysis to ensure working silicon What we need to see: BS/MS/PhD (or equivalent experience) in Electrical or Computer Engineering Minimum 12 years of circuit design experience Strong understanding of SRAM and memory design techniques and macro/block development Ways to stand out from the crowd: Self-motivation, attention to detail, clear data analysis and presentation skills Familiarity with industry tools such as Cadence Virtuoso for schematic and layout, SPICE simulators, waveform viewers Background with developing and using various flows and methodologies, in

Shape the Future with Dun & Bradstreet At Dun & Bradstreet, we believe data has the power to create a better tomorrow. As a global leader in business decisioning data and analytics, we help companies worldwide grow, manage risk, and innovate. Since 1841, businesses have trusted us to turn uncertainty into opportunity. We’re a diverse, global team that values creativity, collaboration, and bold ideas. Are you ready to make an impact and help shape what’s next? Join us! Explore opportunities at dnb.com/careers. We are now looking for a Senior Accountant – General Ledger to join our Finance team in Warsaw, Poland. In this role, you will play a key part in ensuring accurate financial reporting, strong balance sheet governance, and compliance across multiple legal entities, while partnering with stakeholders locally and globally. What You’ll Do As a Senior Accountant – General Ledger, you will be responsible for end‑to‑end accounting activities with a strong focus on general ledger ownership and financial integrity.

At Curai, we believe that access to high-quality healthcare is a fundamental human right, not a privilege. Our mission is to radically transform healthcare delivery by harnessing the power of artificial intelligence and clinical expertise to make care more affordable, accessible, and effective for everyone. Patients interact with advanced AI systems at every step of their care and follow-up. Licensed physicians review each case with the patient for the clinical decision in our integrated virtual clinic. We ground our approach in rigorous research, continuous learning, and a deep commitment to clinical integrity. We focus on making a real impact: improving health outcomes, expanding access to care, and setting new standards for what trustworthy, patient-centered healthcare is. Read some of our latest publications.

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Responsibilities and Duties We are seeking a highly skilled System Tests & Diagnostics Engineer to develop, extend, and integrate specialized silicon validation and diagnostics tools for next-generation AI SoCs. Unlike traditional validation roles focused on executing test plans, this position is responsible for developing the diagnostic software and stress tools that expose hardware failures, characterize silicon behavior, and improve platform observability throughout bring-up and validation. You will work closely with Arm engineers to understand and extend existing diagnostics technologies while developing Graphcore-specific capabilities for future AI hardware. Role Summary You will work with existing Arm-developed diagnostics technologies and extend them to support Graphcore's next-generation AI silicon. You will be responsible for developing system-level diagnostics and stress tools that integrate with an existing framework to detect data integrity, computational correctness, performance, and reliability issues across CPUs, AI accelerators, memory, storage, PCIe, firmware, BMC, and other platform components. Examples include silent data corruption (SDC) tests, power transient stress tools, and platform diagnostics, with opportunities to develop new diagnostics as future hardware capabilities evolve. This role requires close collaboration with hardware architects, firmware enginee