Simulation And Modeling Lead in India

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers.You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU verification or closely related digital design. You know high‑performance out‑of‑order CPU microarchitecture in depth. You work comfortably with RTL, waveforms, logs, and complex debug scenarios. You communicate clearly across design, DV, emulation, and post‑silicon teams. What We Need Plan and drive functional verification for CPU core features and complex microarchitectural scenarios. Develop UVM, assembly, and C/C++ based stimulus, functional models, and coverage for ISA, RISC-V extensions, and un-core components. Debug simulation and emulation regressions using RTL understanding, waveforms, and logs to identify and resolve issues efficiently. Build and enhance coverage models, testbenches, and debug infrastructure to improve verification quality and coverage closure. Collaborate with design, validation, and

We are looking for a talented Senior System Software Engineer to help build NVIDIA Halos, our full-stack safety critical platform for physical AI: autonomous vehicles, humanoids, industrial robots, and intelligent machines that sense, decide, and act in the real world. This role is equally grounded in ISO 26262 functional safety engineering and embedded systems, rich operating systems, virtualization, accelerated computing. If you have a good understanding of System Software development on Real Time OS (RTOS), ARM architecture, Virtualization, and experience with ISO 26262 safety lifecycle, we want to hear from you! We are a leading artificial intelligence computing company and are paving the way with innovations in gaming, visualization, supercomputing, and autonomous vehicle and robotics safety platforms. NVIDIA gives automakers, tier-1 suppliers, automotive research institutions, and startups the power and flexibility to develop and deploy breakthrough artificial intelligence systems for autonomous vehicles. Our unified computing architecture makes it possible to train deep neural networks in the data center on the NVIDIA DGX™, and then seamlessly run them on NVIDIA's Halos platform inside the vehicle. Leading vehicle manufacturers, tier 1 suppliers, mapping and simulation companies, software and sensor providers, and startups around the world are developing on the NVIDIA Halos® platform to deliver the best solutions for the new world of mobility. As a System Software Engineer, you will get an opportunity to work on high-performance NVIDIA edge AI platforms running complex mixed-criticality software stacks across QNX, Linux, hypervisors, safety partitions, accelerators, and real-time AI workloads, and work alongside industry experts in diverse teams and projects. <

We are seeking a Front-End Integration Engineer for the NIC Silicon group. Join our team at NVIDIA's Networking business unit and be part of the innovative build and implementation of the next generation Network Adapter Silicon chips. Contribute to the development of powerful communication devices. What You'll Be Doing: Own and maintain Continuous Integration pipelines. Monitor, complete, and fix daily and nightly CI flows in front-end build areas. These include Lint, Synthesis, Equivalence Checking and Simulation. Automate EDA Flows: Build, develop, and maintain robust automation scripts using Python, Tcl scripting, and Shell to integrate EDA tools (Synopsys, Cadence) into automated build pipelines. Manage Perforce Integration: Maintain multi-IP branch/stream strategies, manage workspace specs, complete hardware build drops, and handle release labels/tags in Perforce (Helix Core). Support Engineering Teams: Act as the primary point of contact for RTL and verification engineers to debug flow crashes, bottlenecks, environment setups, and CI failure reports. Enforce Quality Gates: Implement automated check-in and change list triggers to run sanity checks, linting, and style enforcement before code is committed to main streams. Optimize Infrastructure: Monitor compute farm resources (LSF) and storage usage to reduce pipeline runtime and improve overall execution efficiency. What We Need to See: Experience: 2&#43; years of hands-on industry experience in ASIC/SoC front-end integration, CAD, or EDA flow automation. Education: Bachelor’s degree or Master’s degree or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Perforce Expertise: Strong hands-on experience managing Perforce (P4 / Helix Core) streams, workspace specs, c

NK Securities Research is a leading financial firm that leverages cutting edge technology and sophisticated algorithms to trade the financial markets. Founded in 2011, we have gained invaluable experience in the field of High Frequency Trading across different asset classes. With a focus on innovation, entrepreneurship, and collaboration, we aim to foster a dynamic work environment that reflects a startup culture. Role Overview As an FPGA Developer, you will design, implement, and rigorously test RTL (Register-Transfer Level) designs to power our high-frequency trading strategies. Your contributions will play a pivotal role in reducing system latency and enhancing performance, directly impacting trading outcomes. Key Responsibilities Design and Implementation: Develop high-performance RTL designs using VHDL or Verilog for FPGA-based systems. Optimize hardware implementations for ultra-low latency and high throughput. Testing and Debugging: Perform thorough functional and timing testing of RTL designs, ensuring adherence to specifications. Debug and resolve issues using FPGA debugging tools such as SignalTap, ChipScope, or ModelSim. Collaboration and Documentation: Work closely with hardware and software teams to ensure seamless integration of FPGA solutions with the Software Trading Stack. Maintain clear and comprehensive documentation of designs, test cases, results and benchmarks Qualifications Technical Skills: RTL Development: Strong fundamentals in digital logic design, Boolean algebra, FSMs and synchronous design. Proficiency in VHDL or Verilog/SystemVerilog, with a strong focus on efficient and optimized designs. FPGA Tools: Hands-on experience with industry-standard tools such as Xilinx Vivado. Testing and Verification: Expertise in writing testbenches and conducting simulation-based verification. Familiarity with static timing analysis and achieving timing closure. Familiar with CocoTB or any similar testing setup. Debugging: Proficiency in GHDL synthesis a

Job Details: Job Description: We are seeking an experienced Analog Design and Infrastructure DA Manager to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs..The ideal candidate combines deep analog/mixed-signal design flow and e-test structure development expertise with strong infrastructure leadership and disciplined configuration/data management practices. Key Responsibilities-1. Analog Design Environment and Flow Management-Own and maintain analog and mixed-signal design flows using platforms such as Virtuoso ,Develop and maintain schematic, layout, verification, and extraction flows (LVS, DRC).Support simulation environments including HSPICE, Corner analysis.Drive automation and methodology improvements to reduce turnaround time and increase design robustness. 2. Infrastructure and Compute Management Oversee Linux-based DA infrastructure including compute farms, storage systems, and license servers (FlexLM). Manage LSF/grid environments and job scheduling systems. Ensure scalability, system monitoring, high availability, and performance optimization. Partner with IT on hardware lifecycle planning, cloud integration, and disaster recovery. Maintain secure, access-controlled design environments aligned with IP protection policies. 3. Design Data, Manifest and Configuration Management Design Data Governance Manage large-scale analog design libraries, hierarchical database structures, and technology libraries. Define backup, archival, and retention policies for tapeout-critical data. Implement data integrity validation and corruption prevention controls. Oversee distributed stor

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking an experienced and motivated System IP RTL Design Lead to drive the definition and implementation of complex datacenter class IP for our next-generation semiconductor products. The ideal candidate possesses a deep understanding of System IP and SoC architecture, IP integration challenges, and is adept at leading a design team to deliver high-quality, scalable IP solutions. This role requires strong hands-on technical leadership, excellent communication skills, and a proven track record in the successful delivery of silicon IP. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned IP / SoC design leader with 20+ yrs of strong expertise in complex SoC architectures, high-speed protocols, and large-scale IP integration. Skilled in RTL design and debug (Verilog/SystemVerilog) with hands-on experience using industry-standard tools for simulation, synthesis, lint, CDC, and power analysis on high-frequency designs. Experienced in driving microarchitecture decisions, authoring design specifications, and performing complex PPA trade-off optimizations. A proactive problem so

As an FEA Analyst (ANSYS) will be responsible for performing finite element analysis and simulations to assess the structural integrity and fatigue life calculation various wind turbine components products. The role involves collaboration with cross-functional teams to enhance designs using advanced simulation tools. Source: Adani Group | Job ID: 50348

Job Overview: We are looking for a Senior GenAI Developer to design, build, and productionize agentic AI systems—LLM-powered agents that can plan, use tools, orchestrate workflows, and operate reliably under enterprise constraints. You will own key parts of the agent architecture (planning, tool use, memory, evaluation, safety/guardrails, and observability) and deliver end-to-end solutions across RAG, function/tool calling, multi-agent coordination, and scalable deployment. Key Responsibilities Design and implement agentic systems: single-agent and multi-agent architectures (planner/executor, supervisor-worker, routing, reflection, critique, task decomposition). Build robust tool-using agents: function calling, tool schemas, tool authorization, retries, rate limiting, and sandboxing. Implement RAG + memory patterns: retrieval strategies, hybrid search, context assembly, long-term memory, and grounding/citation behaviors. Develop workflow orchestration for agent execution (state machines/graphs), concurrency controls, and deterministic execution where possible. Productionize GenAI services: APIs, background jobs, streaming responses, caching, and cost/latency optimization. Establish agent evaluation: golden sets, simulation-based evals, LLM-as-judge with mitigations, task success metrics, regression testing. Build observability and safety: tracing, token/tool telemetry, anomaly detection, prompt injection defenses, data leakage prevention, policy enforcement. Collaborate with product, security, and platform teams to deliver enterprise-ready solutions and integrate with internal systems (data, identity, workflow). Mentor engineers, set coding standards, and contribute to architecture reviews and technical roadmaps. Required Qualifications 6+ years software engineering experience; 2+ years building LLM/GenAI systems in production. Strong programming skills in Python (required) and/or TypeScript/Node.js. H

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE Drive the mission-critical quality strategy for the industry’s most innovative, high-performance storage array platform. In this pivotal engineering leadership role, you will scale systems testing, feature interoperability, and test automation to ensure zero-downtime resilience for global enterprise applications. Partnering directly with cross-functional development, support, and escalation engineering teams, you will champion a customer-first quality model across physical hardware and cloud-native environments (Cloud Block Store, CloudSnap). This position elevates product reliability and shapes how cutting-edge software resilience is delivered at scale. WHAT YOU'LL DO Define & Execute Quality Strategy: Ownership of end-to-end system test designs, focusing on feature interoperability at scale to guarantee zero-downtime performance across enterprise and cloud environments. Build High-Impact Automation & Tooling: Design and deploy automated test workflows and triage tooling to accelerate defect detection, drastically reducing execution friction across thousands of automated test suites. Real-World Customer Simulation: Replicate complex customer deployment architectures and enterprise application workflows to validate real-world resilience, fault tolerance, and resilience against failure domains. Root-Cause Resolution & Continuous Improvement: Partner directly with escalation and support teams to reproduc

Who we are Graviton Research Capital is a privately funded quantitative trading firm. We trade across a multitude of asset classes and trading venues using a diverse range of concepts, from time series analysis and stochastic models to machine learning and statistical inference. We analyse terabytes of data to identify pricing anomalies and drive innovation in financial markets. Role Overview We are looking for a Program Manager who thrives at the intersection of rigorous engineering and predictable delivery. You will not just "manage tasks" — you will orchestrate the development lifecycle for mission-critical systems. Your goal is to ensure that our elite engineering teams can focus on high-performance code while you own the execution strategy, dependency mapping, and release discipline. Key Responsibilities Lead Agile ceremonies (Sprint Planning, Stand-ups, Retrospectives) tailored for deep-tech engineering teams. Transform high-level trading requirements into granular, executable backlogs. Own capacity planning and burn-down metrics to provide high-visibility delivery timelines. Navigate the complex interplay between engineering teams (e.g., Connectivity, Core Infrastructure, Simulation) to prevent bottlenecks. Build and maintain advanced Jira dashboards, automated roadmaps, and Confluence documentation that serve as the "single source of truth" for stakeholders. Proactively identify technical debt, architectural blockers, or resource gaps that threaten release stability. Continuously refine Agile methodologies to suit low-latency, performance-sensitive development cycles (where "Definition of Done" includes rigorous performance benchmarking). Eligibility & Required Skills 5+ years of experience as a TPM, Program Manager, or Scrum Lead in a product-engineering environment (HFT, FinTech, Networking, or Kernels/Systems). A strong grasp of the software development lifecycle for high-performance systems. While you won't write code, you must understand concepts li

Their responsibilities include developing project plans, managing budgets and timelines, conducting site assessments, and providing technical guidance on acoustical materials and solutions. Acoustical Project Managers often perform or review sound measurements and simulations to address issues like noise control, sound insulation, and audio quality. They play a key role in ensuring comfortable, functional, and compliant acoustic environments. They coordinate with engineers, and clients to ensure that acoustical requirements are met throughout the design and construction process.

Job Title: Lighting Designer (AutoCAD + DIALux) Location: Jubilee Hills, Hyderabad Key Responsibilities: • Design and plan lighting layouts for commercial, industrial, and architectural projects using AutoCAD and DIALux. • Create photometric calculations, 3D models, and lighting simulations. • Collaborate with architects, engineers, and clients to finalize designs. • Prepare lighting proposals, drawings, and technical specifications. • Ensure designs meet standards and regulations (BIS, IES, etc.). Requirements: • B.E./B.Tech (Electrical/Illumination) or equivalent. • 1-3 years of experience in lighting design (preferably with AutoCAD and DIALux). • Proficiency in lighting calculations, fixture selection, and photometry. • Strong understanding of lighting concepts and design principles. We have 5 openings across Kokapet and Madhapur

We are seeking an experienced professional to lead and execute enterprise-wide cybersecurity training and awareness initiatives. The role focuses on enhancing employee cyber hygiene, conducting phishing simulations, and building structured training programs across cybersecurity domains. Source: Adani Group | Job ID: 54025

The role of the Vocational Training Officer focuses on managing processes to meet production targets while prioritizing safety training initiatives and compliance. They maintain records, conduct simulations, and facilitate effective training for new officers and employees to foster a culture of safety and productivity in the mining environment. Source: Adani Group | Job ID: 55064

The role of the Vocational Training Officer focuses on managing processes to meet production targets while prioritizing safety training initiatives and compliance. They maintain records, conduct simulations, and facilitate effective training for new officers and employees to foster a culture of safety and productivity in the mining environment. Source: Adani Group | Job ID: 51855