Software Engineer Application Platform Salary India Jobs

What We Do At GoGuardian, we’re helping build a future where all learners are ready and inspired to solve the world’s greatest challenges. Our award-winning system of learning solutions is purpose-built for K-12 and trusted by school leaders to promote effective teaching and equitable engagement while helping empower educators to keep students safe. What It’s Like to Work at GoGuardian We are an outcomes-focused learning company with a steadfast focus on improving learning environments, one classroom at a time. Working with us means joining a remote team of diverse, committed, mission-driven employees who are inspired by our vision, dedicated to our customers, and ready to roll up their sleeves. Guardians put their heads together to solve problems, learn together from experiments that fail, and stand together by their work with full accountability. We balance our diligence with an inclusive culture that invites everyone to bring their whole self to work. Join us and learn why “I love the people here” is one of the most frequent comments we hear from Guardians. What We Do At GoGuardian, we’re helping build a future where all learners are ready and inspired to solve the world’s greatest challenges. Our award-winning system of learning solutions is purpose-built for K-12 and trusted by school leaders to promote effective teaching and equitable engagement while helping empower educators to keep students safe. The Role We’re looking for a Senior Site Reliability Engineer (SRE) to help design, scale, and maintain the infrastructure that powers our core products and services. In this role, you’ll collaborate with engineering teams to drive operational excellence, optimize system performance, and ensure high availability across production environments. This position sits on Tech Foundation, a team that manages core cloud infrastructure, shared data services, and developer tooling to empower our product teams to deliver software efficiently and secu

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. As a PCB Power Design Engineer, you will design and optimize power distribution systems for Tenstorrent’s next-generation AI accelerator cards, balancing performance, area, cost, and reliability. You will contribute across the full power design lifecycle, from component selection and simulation through board bring-up, validation, debugging, and production readiness. Working closely with hardware, firmware/software, thermal, mechanical, and validation teams, you will help deliver robust power architectures for high-performance AI systems. This role is hybrid, based out of Toronto, Canada. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An electrical engineer with experience designing, analyzing, and debugging power distribution systems for high-performance or high-power products. A hands-on engineer who enjoys moving from schematics and simulations into lab bring-up, testing, troubleshooting, and design validation. A systems-oriented collaborator who can work effectively across hardware design, firmware/software, thermal, mechanical, and validation teams. A detail-oriented problem solver who balances electrical performance, power integr

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans the entire quantum compute stack while harnessing the power of Intel's 18A process and design infrastructure. We are seeking an exceptional Quantum Design Engineer to join our pioneering quantum computing team. In this position, you will be joining a team of incredibly talented engineers focused on the challenging task of scaling our quantum computing chips to millions of qubits. Here you will be involved in all aspects of the qubit chip process from initial conception through Process-Design-Kit definition, design execution and tapeout, along with ensuring silicon runs smoothly in fab and final system integration. You'll work closely not only with our qubit, control, system integration, and software/algorithms teams, but also with teams in Foundry lithography, process and design. You'll be working at the intersection of cutting-edge semiconductor technology and quantum physics, creating solutions that push the boundaries of what's possible in computing. Ready to help build the future of quantum computing? Apply now and be part of this extraordinary journey Key Responsibilities • Work alongside lithography, process integration, measurement, and PDK engineers to establish qubit processes and design rules • Architect qubit and readout element standard cell design and autom

About the Team OpenAI’s IT organization supports the mission of deploying artificial general intelligence (AGI) for the benefit of all. Our team is committed to providing seamless technological support and solutions to ensure that all OpenAI employees are well-equipped and connected. This enables them to contribute effectively towards our AI research, corporate operations and product initiatives. About the Role As an ITAV Operations Engineer at OpenAI, you will administer and troubleshoot conference room AV, video conferencing, background music, digital signage, and other ITAV-owned systems. You will serve as the technical bridge between our support vendors and ITAV Engineering, resolving escalations that require internal access, administrative permissions, or deeper technical investigation. You will maintain reliable configurations, execute changes using established standards, and turn recurring issues into improvements to systems, documentation, and automation This is an in-office role and will require 5 days a week in our San Francisco office. Travel 30% of the time to support ITAV systems, technical changes, and operational readiness. International travel is required. In this role, you will: Set up, configure, administer, and maintain conference room AV, video conferencing, background music, digital signage, and other ITAV-owned systems. Resolve vendor escalations that require internal administrative access or technical expertise, owning diagnosis, remediation, and verification of service restoration. Manage assigned ITAV installation and commissioning scope for office builds, refreshes, and moves, adds, and changes using established standards, and verify that completed systems are ready for ongoing operation. Serve as the technical bridge between vendors and ITAV Engineering, providing clear diagnostic evidence and escalating issues that require changes to system designs or engineering standards. Execute software updates, configuration changes, equipment replac

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron-Boise, ID, we are undergoing a historic $15 billion investment in semiconductor manufacturing; construction began in early 2023, with DRAM production slated for the second half of the decade. As a leader in the semiconductor industry, we build solutions that encourage and transform technology. With plans to invest more than $150 billion globally over the next decade in groundbreaking manufacturing, we are looking for hardworking people to join our Boise expansion team and give to the growth and innovation of the semiconductor industry. ID1 High Volume Manufacturing Equipment Engineer is responsible for monitoring, sustaining, and improving the equipment while working in partnership with process team members and area engineers. In this position you will supervise tool performance, schedule and perform preventative maintenance on assigned tool sets, and use mechanical, electronic and PC/software skills to solve and repair equipment issues. They are also required to assist with equipment installations, engineering tests, build and modify equipment procedures, increase tool uptime through systematic problem solving and quality workmanship, and thoroughly document all maintenance. This is a hands-on equipment focused role with time spent in the fabrication facility. Responsibilities: Safely identify, handle, and work with chemicals and associated hazards in the work area. Recognize and respond appropriately to safety alarms and events, including EES, fire alarms, MDA, and ERT notifications. <l

Senior Container Security Engineer – CVE Remediation & Image Hardening About the Role We are looking for a hands-on Senior Container Security Engineer to lead vulnerability remediation and image hardening across Linux-based container environments. This role focuses on deep operating system and container security engineering rather than simple vulnerability scanning. You will analyze, remediate, rebuild, harden, and continuously optimize container images used in modern cloud-native platforms. You will work closely with platform engineering, DevOps, infrastructure, and security teams to build automated remediation pipelines, reduce the attack surface, and deliver production-ready hardened images. What You’ll Do - Own end-to-end CVE remediation across Linux-based container images. - Analyze vulnerabilities across OS packages, libraries, runtimes, and dependencies. - Patch, rebuild, validate, and maintain hardened container images at scale. - Reduce attack surface by removing unnecessary packages, binaries, services, and dependencies. - Build and scale automated remediation pipelines for continuous image patching. - Improve image security posture while minimizing operational disruption. - Generate, validate, and maintain SBOMs to support supply chain visibility and compliance. - Integrate remediation workflows into CI/CD and GitOps pipelines. - Optimize image size, startup performance, and operational efficiency. - Research emerging Linux, container, Kubernetes, and software supply chain threats. - Troubleshoot complex dependency, package compatibility, and runtime security issues. - Help define internal standards for hardened images and secure software delivery. What You Bring - 5+ years of experience in Linux systems engineering, platform engineering, DevSecOps, security engineering, or SRE. - Deep understanding of Linux distributions (Debian, Ubuntu, Alpine, RHEL). - Strong hands-on experience with Docker, Kubernetes, and

Who We Are HP IQ is HP’s new AI innovation lab. Combining startup agility with HP’s global scale, we’re building intelligent technologies that redefine how the world works, creates, and collaborates. We’re assembling a diverse, world-class team—engineers, designers, researchers, and product minds—focused on creating an intelligent ecosystem across HP’s portfolio. Together, we’re developing intuitive, adaptive solutions that spark creativity, boost productivity, and make collaboration seamless. We create breakthrough solutions that make complex tasks feel effortless, teamwork more natural, and ideas more impactful—always with a human-centric mindset. By embedding AI advancements into every HP product and service, we’re expanding what’s possible for individuals, organisations, and the future of work. Join us as we reinvent work, so people everywhere can do their best work. About The Role HP IQ's Wireless Technology Team works cross-functionally with Electrical Engineering, Software, Mechanical Engineering, Product Design, Industrial Design, Program Management, and Operations to develop next-generation wearable and AI-connected products. As a Lead RF Systems & Desense Engineer, you will own the RF system architecture from concept through mass production. You will lead RF integration across Wi-Fi, Bluetooth, UWB, NFC and emerging wireless technologies while driving RF desense, coexistence, and wireless performance for highly integrated products. What You Might Do Lead RF system architecture and integration for wearable and mobile platforms. Own RF desense investigations and mitigation across the product lifecycle. Define RF specifications, link budgets, validation plans and performance targets. Lead coexistence strategy for Wi-Fi, Bluetooth, UWB, NFC and other radios. Partner with antenna, EE, FW, ME and silicon vendors to optimize total wireless performance. Perform CST and ADS simula

About Forma.ai: Forma.ai is a Series B startup that's revolutionizing how sales compensation is designed, managed and optimized. We handle billions in annual managed commissions for market leaders like Edmentum, Stryker, and Autodesk. Our growth has been fuelled by our passion for fundamentally changing and shaping how companies use sales intelligence to drive business strategy. We’re welcoming equally driven individuals who are excited about creating something big! About the Team Engineers on this team construct our rules-based calculating engine for processing sales commissions. This might sound simple if you have never been exposed to sales comp plans, it is not! We are low on meetings, high on accountability. Most of the team are in EST time zone but we have a few located in PST and Central as well. We are far from maintenance / progressive evolution in many areas, there is a lot of room to make a big impact in the overall design. What you’ll be doing Reporting to the Manager of Data Platform, you will play a critical role in the evolution of our Spark based data platform. You'll lead development efforts for our complex, data-rich platform features while being an example to the team of code quality and thoughtful software design. You will be working on the most challenging code at Forma. As a Staff Engineer, you are expected to operate with a high degree of ownership and trust. This includes proactively identifying architectural risks, surfacing edge cases or constraints others may not see, and advocating for improvements that strengthen the long-term integrity of the system. We value engineers who bring forward thoughtful perspectives - even when they challenge assumptions - and who help the team see around corners. You will: Design and evolve backend services that power product workflows. Architect data models representing hierarchical & graph structures, relationships, and large-scale enterprise datasets. Build

At Breeze, we're building the AI-powered infrastructure layer for global commerce, making it radically simpler for businesses to sell, get paid, and operate across markets. We go far beyond traditional payment processing. Breeze combines global payments, AI, stablecoins, and a Merchant of Record-like model to take on the complexity businesses typically manage themselves, including compliance, risk, fraud, chargebacks, reconciliation, and customer support. Our goal is simple: let businesses focus on building and selling great products while Breeze handles the complexity behind getting paid. Backed by Sequoia Capital , Multicoin Capital , and The Chainsmokers , Breeze is a successful, rapidly growing, and exceptionally well-capitalized company. We have the runway to think long term while remaining early enough that every person joining today can have a meaningful impact on what we build. We are hiring a Staff Machine Learning Engineer, Risk! As our Staff Machine Learning Engineer, Risk, you'll lead the evolution of our ML platform for payment risk, building the production-grade capabilities behind feature engineering, model training, deployment, monitoring, and continuous improvement. Risk decisions sit at the center of our business, and you'll own how those models get built, shipped, and kept healthy. This role reports to the CTO. You'll work closely with Risk, Software Engineering, and Data Engineering, and you'll be the senior technical voice for ML on the risk team. We're looking for someone who thrives in fast-moving environments, wants meaningful ownership, and is excited to build rather than simply maintain. What You'll Do Design and build ML infrastructure for payment risk detection, using Databricks as the core platform, in close partnership with software and data engineers. Bring structure to the team's ML environment: feature pipelines, versioning, job orchestration, and monitoring. Design and productionize models rather than just prototype them, including

About PayPay India PayPay, a fintech company providing a service enjoyed by over 75 million users since its launch in 2018 in Japan. The company is now home to a very diverse team of members from more than 50 countries. We grew to a team of several thousand employees in Japan but are far from over. We are still in the Day 1. Every day, new members join us from all over the world to create new value and deliver it to society. Why India ? To build our Payment services, we got technical cooperation from Paytm (A large payment service company in India). And based on their customer-first technologies , we created and expanded the smartphone payment service in Japan. Therefore, we have decided to establish a development base in India, because it is a major IT country with many talented engineers, as evidenced by the fact that cutting-edge mobile payments can continue to be generated. OUR VISION IS UNLIMITED We dare to believe that we do not need a clear vision to create a future beyond our imagination. PayPay will always stay true to our roots and realise a vision (future) that no one else can imagine by constantly taking risks and challenging ourselves. With this mindset, you will be presented with new and exciting opportunities on a daily basis and have the opportunity to grow and reach new dimensions that you could never have imagined. AI-First Culture at PayPay At PayPay, we believe the future of software development is AI-augmented engineering. Every engineer is expected to actively leverage AI tools for code reviews, testing, documentation, debugging, and productivity improvements. AI is not optional — it is a mandatory part of our daily engineering workflow. Candidates must demonstrate both hands-on experience and the right mindset to integrate AI effectively into their workflow, while maintaining the engineering rigor, ownership, and problem-solving skills that only humans can provide. Job Description PayPay India&nb

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to define and implement RTL for high-performance CPUs. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in CPU microarchitecture with expertise in Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache or Datapath. Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis. Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments. Background in microarchitecture definition, design specification, and performance-driven trade-off analysis. What We Need Own RTL design and microarchitecture development for a portion of a CPU block of a high-performance RISC-V CPU. Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals. Use innovative techniques to optimize power, performance, and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to lead pre-silicon verification of the Beowulf SoC, with focus on the Compute Subsystem (CSS), DDR memory subsystem, and Fabric NoC. This role will drive coverage, coherency, memory traffic, connectivity, error handling, and bring-up features critical to silicon success. This role is hybrid, based out of Boston, MA; Toronto, ON; or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Deeply curious about SoC architecture, compute systems, DDR behavior, and Fabric NoC/interconnect verification. Expert in UVM, SystemVerilog, coverage-driven verification, assertions, and subsystem-level debug. Experienced in verifying compute subsystems, DDR controllers and PHY-facing logic, NoC/interconnect protocols, coherency, ordering, and data movement. Comfortable with reset, power management, error handling, performance, and high-concurrency system scenarios. Proactive, detail-oriented, and effective in cross-functional technical discussions. Familiar with Python, C/C++, Tcl, CocoTB, or similar verification automation tools. What We Need Develop and own scalable verification environmen

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to drive infrastructure for performance analysis, correlation and verification. You’ll work on a CPU based on RISC-V ISA, collaborating with core architects and RTL teams to deliver a highly efficient and performant design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Strong problem solver who can identify complex issues, develop practical solutions, and drive them through implementation. Enjoy building tools and improving the infrastructure, workflows, and methodologies that make CPU development more efficient. Skilled in C++ and Python, with experience using industry-standard compilation, simulation, and emulation tools. Experience with verification infrastructure and methodologies along with knowledge of high-performance CPU architecture and microarchitecture. Proficient in debugging RTL and logic across multiple design hierarchies and pre-silicon environments. What We Need Join a team driving improvements in CPU microarchitecture, verifying performance, and correlating results between RTL and the performance mode

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Join Tenstorrent and help bring next-generation AI accelerator technology from silicon bring-up to production. You’ll work at the forefront of hardware innovation, diagnosing complex issues across chips, systems, firmware, and software while collaborating with some of the brightest engineers in the industry. This role offers the opportunity to solve challenging technical problems, build impactful debug solutions, and directly influence the reliability and performance of cutting-edge AI compute platforms. This role is hybrid, based out of Toronto, Canada. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on hardware debug engineer who thrives on solving complex, cross-functional problems at the intersection of silicon, firmware, and software. A curious and analytical problem solver who enjoys digging into failures, identifying root causes, and driving issues from initial discovery through resolution. An engineer with strong post-silicon validation and bring-up experience who is comfortable working in the lab and getting deep into system-level behavior. Someone who enjoys building tools, improving debug methodologies, and creating

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to validate the System Management Controller (SMC) and enable seamless multi-chip integration. In this role, you will design and execute tests, build infrastructure, and debug issues across chiplet-based SoCs. You’ll have the opportunity to work with remote mentorship while contributing to the foundation of scalable multi-die systems. This role is hybrid, based out of Toronto, Ontario, Boston, MA or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Proficient in SystemVerilog, SV-UVM, Python, and C/C++ with strong verification skills. Experienced in writing test plans, building infrastructure, and debugging hardware/software flows. Comfortable working with remote mentorship and distributed teams. Familiar with AI-assisted tools like Copilot, Cursor, and Claude to accelerate verification. What We Need Develop and maintain SMC tests and supporting DV infrastructure. Write, execute, and track test plans for chiplet and multi-chip SoC designs. Use C/C++ to develop tests compiled, loaded, and executed directly on the DUT. Triage, analyze, and debug issues in clos