Yield Enhancement Engineer Jobs

Job Details: Job Description: Embark with us on a journey of growth and transformation as we create exceptionally engineered technology and bring AI everywhere. As a valued team member, your adaptability and attention to detail will contribute to our drive for results and relentless pursuit of quality, ensuring we meet our customers' needs with precision. Join us and build on our legacy of innovation and collaboration as we deliver world‑changing technology that improves the life of every person on the planet. Life at Intel: https://jobs.intel.com/en/life-at-intel This position is in the Intel Mask Operations within the Logic Technology Development team working in one of the most advanced semiconductor process technologies in the world. In this position the engineer will be an integral contributor to the ongoing production of photolithography masks for Intel's leading-edge silicon manufacturing solutions. In this position, you will work on-site, in a dynamic and collaborative environment solving complex and challenging technical problems on sophisticated manufacturing processes and equipment. As an IMO Module Development Engineer, the responsibilities may include but not limited to: Process equipment installation and development. Equipment maintenance, management of troubleshooting activities, regular monitoring of process performance, defect analysis and reduction. Drives improvements on quality, reliability, cost, yield, process stability/capability, productivity, and safety/ergonomics. Working with cross functional teams to solve technical process and defect issues. Plans and conducts experiments to fully characterize the process throughout the development cycle. Establishes control systems to optimize and sustain production performance. D

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Intro: The Advanced Packaging Technology Development (APTD) department at Micron Technology is advancing next-generation packaging technologies that enable the performance and scalability requirements of tomorrow’s AI and high-performance computing applications. Our team brings together experts in process integration, materials engineering, and semiconductor development to solve complex technical challenges and turn new ideas into production-ready solutions. Join us and help shape the future of advanced memory and packaging technology! Position Overview: As a Process Integration Engineer for Advanced Packaging, you will play a key role in developing and integrating advanced package architectures, including 2.5D, 3D stacking, HBM, and hybrid bonding technologies. You will work across engineering disciplines to develop new processes, improve performance and yield, and support the transfer of emerging technologies into manufacturing. This is an opportunity to contribute to innovative products while working on some of the industry's most advanced packaging solutions. Responsibilities: Develop and optimize advanced packaging technologies, including 2.5D/3D integration, HBM, hybrid bonding, and advanced interconnects Design and execute experiments to qualify materials, process flows, and design rules for new package architectures Analyze yield, performance, and defect data to identify process improvements using SPC and advanced analytics Drive

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our Vision Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever. Micron is advancing a historic $15 billion investment in semiconductor manufacturing in Boise, Idaho, with DRAM production planned for the second half of the decade. As a global leader in memory and storage solutions, Micron is investing more than $150 billion worldwide over the next decade to expand leading-edge manufacturing capabilities and drive innovation across the semiconductor industry. Join the Boise expansion team and help build the future of semiconductor manufacturing. You will work alongside experienced engineers to develop advanced processes, solve complex manufacturing challenges, and support the production of technologies that power everything from artificial intelligence to next-generation computing systems. Position Overview As a PCVD Process Engineer , you will contribute to the development, optimization, and sustainment of semiconductor manufacturing processes. You will gain hands-on experience in a state-of-the-art fabrication environment, partnering with teams to improve yield, quality, reliability, and productivity. This role offers an outstanding opportunity to apply engineering fundamentals, build technical expertise, and develop a career in advanced semi

Senior Tooling Engineer About the Role The Senior Tooling Engineer is responsible for leading and optimizing tooling development from initial tooling design through mass production sustaining with ODMs (Original Design Manufacturers) and CMs (Contract Manufacturers). This role plays a critical part in ensuring that tooling design meets strict quality, throughput, and cost targets while driving Design for Manufacturing (DFM) and Design for Assembly (DFA) in close collaboration with internal Mechanical Engineering, Quality, and Supply Chain teams. The ideal candidate possesses deep hands-on expertise in plastic injection molding, sheet metal stamping, die casting, hydroforming, and tooling fabrication processes, along with proven cross-functional communication and supplier management skills. Your Daily Impact at Peloton DFM & Engineering Collaboration: Collaborate with cross-functional engineering teams (ME, ID, Hardware, Quality) to conduct robust DFM/DFA reviews, guiding process selection, material selection, and tooling qualification plans. Tooling Design & Validation: Lead technical reviews for tooling designs, mold layouts, and drawings (including Moldflow simulation, gate placement, cooling, parting lines, and ejector pin layouts). Validate tooling designs with suppliers and toolmakers to proactively troubleshoot issues. NPI Execution: Drive tooling deliverables across all Hardware Product Development phases (Alpha, EVT, DVT, PVT) to support key NPI programs, ensuring timely OK2TOOL and OK2FAB approvals. Supplier & ODM/CM Management: Work closely with ODMs and CMs to manage tooling build progress, trial runs (T1/T2), root cause troubleshooting, and yield improvements on the manufacturing floor. Maintenance & Tooling Audits: Establish and maintain supplier-facing tooling maintenance standards and asset management procedures. Conduct on-site supplier and tooling audits to ensure quality maintenance and mold longevity. PPAP & Quality Alignment:

The mission of The New York Times is to seek the truth and help people understand the world. That means independent journalism is at the heart of all we do as a company. It’s why we have a world-renowned newsroom that sends journalists to report on the ground from nearly 160 countries. It’s why we focus deeply on how our readers will experience our journalism, from print to audio to a world-class digital and app destination. And it’s why our business strategy centers on making journalism so good that it’s worth paying for. About the Role NYT Wirecutter is looking for a Senior Manager, Revenue Analytics to power our business strategy. Your core mandate is to increase audience monetization across our primary businesses—Affiliate, Advertising, and E-commerce—ensuring we preserve long-term audience trust. As a player-coach role, you will lead a team of analysts and partner closely with Revenue, Product, and Marketing leads to establish KPIs, run conversion experiments, and build attribution frameworks that scale revenue. You will report to the Executive Director, Data Analytics. Responsibilities You will lead, mentor, and onboard a team of two direct reports, nurturing their career growth You will analyze affiliate revenue drivers (e.g., merchant commissions, EPC, conversion rates, and partner yield) across all content touch points. You will be the analytics lead for the newly launched Wirecutter Store, reporting on unit economics, merchandise performance, cart funnel analytics, order value (AOV), and customer acquisition/repeat purchase metrics You will partner with Ad Ops and Advertising teams to track ad yield (RPM, eCPM), fill rates, and ad unit viewability, balancing display and custom content revenue against user experience and page speed You will evaluate trade-offs between affiliate links, ad placements, and Wirecutter Store product placements on site, creating a holistic monetization framework to maximize total revenue per user. You will lead recur

Job Details: Job Description: The Role and Impact As a Physical Design Engineer, you will play a critical role in driving the development of cutting-edge technologies at Intel. You will work hands-on to deliver high-performance physical designs, ensuring the successful integration of advanced semiconductor technologies. Your work will directly impact Intel's product innovation, addressing complex challenges in power, performance, and area optimization to shape the future of computing architectures. From synthesis to sign-off, your contributions will enable Intel to meet ambitious design goals and deliver transformative solutions to the market. Business Group This role is part of Intel's Corporate Technology Office (CTO), a dynamic group dedicated to advancing the company's technological leadership and innovation. The group focuses on developing foundational technologies, architectures, and methodologies that drive Intel's product roadmap and enable breakthrough computing solutions. Collaborating with cross-disciplinary teams, the CTO plays a pivotal role in delivering impactful designs that support Intel's broader mission of creating world-changing technology. Key Responsibilities - Drive RTL-to-GDS design convergence using advanced synthesis and place-and-route tools targeting performance, power, and area (PPA) goals. - Deliver block-level physical design, including closure of backend flows, electrical requirements, and enhancing silicon yield. - Collaborate with CAD and physical design methodology teams to adopt industry-leading tools and optimizations for custom designs. - Execute physical implementation tasks such as floor planning, bus/pin placement, power/clock distribution, congestion analysis, timing closure, IR drop analysis, and physical verification. - Debug timing, EM/IR, LVS, and DRC violations, and driv

Job Details: Job Description: The Role and Impact Join Intel as a Module Engineer, where you will play a pivotal role in enhancing the production of advanced integrated circuits. In this position, you will own and optimize high-volume manufacturing equipment and processes, ensuring precision and minimizing defects. Your contributions will directly impact manufacturing efficiency, quality, and scalability, enabling Intel to maintain its leadership in semiconductor innovation. Business Group The role is part of Intel's Assembly Test Manufacturing (ATM) division, which serves as the backbone of Intel's back-end manufacturing operations. ATM supports Intel's diverse portfolio of products across key business segments, including client, server, automotive, and connectivity. The group focuses on advanced packaging and manufacturing technologies to deliver competitive solutions, aligning with Intel's IDM 2.0 strategy to drive innovation and global leadership. Key Responsibilities Own and optimize high-volume manufacturing equipment and processes to achieve production efficiency, quality, and cost goals. Conduct tests and measurements to control critical dimensions and minimize defectivity in production lines. Recommend and implement modifications to improve operational efficiencies, manufacturing techniques, and output performance. Expand high-volume manufacturing capacity to demonstrate technology capabilities and ensure seamless transfer to global manufacturing sites. Execute equipment maintenance, repair activities, and continuous improvement initiatives aligned with safety, quality, productivity, and yield metrics. Develop systems for excursion prevention and identify discrepant material or activities within equipment and processes. Manage equipm

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join Our Team as a STAFF ENGINEER, TDT PD CMP At Micron, we are driven by the pursuit of excellence and innovation. As a Chemical Mechanical Planarization (CMP) Process Development Engineer, you will play a key role on our Technology Development Taiwan (TDT) CMP team. You will contribute to the progress of our innovative DRAM technology. If you have a passion for semiconductor development and enjoy working in a dynamic and collaborative environment, we invite you to join us in defining the future of the semiconductor industry! Key Responsibilities Develop and refine CMP processes to support advanced DRAM technology acceleration. Collaborate with diverse teams to develop new outstanding semiconductor devices. Perform rigorous process characterization, develop new consumables, and evaluate new hardware. Conduct groundbreaking research and innovate to contribute to Micron’s extensive patent portfolio. Drive continuous process and efficiency improvements to meet yield, quality, and cycle time requirements. Direct and manage CMP consumables and equipment suppliers. Plan and complete well-designed experiments, presenting results in clear and concise reports. Minimum Qualifications Proficiency in both Chinese and English languages. Expertise in CMP process development. Hands-on experience with CMP polishing equipment, including familiarity with equipment operation, optical metrology, profilometry, common polishing

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Vice President, Boise Front End Manufacturing Operations Location: Boise, Idaho Reports To: Senior Vice President, Global Front End Operations Position Summary Reporting to the Senior Vice President of Global Front End Operations, the Vice President, Boise Front End Manufacturing Operations is responsible for the overall leadership, performance, and strategic direction of Micron's Boise front-end manufacturing operations. This leader owns the safe, efficient, and predictable execution of all manufacturing activities while ensuring alignment with company objectives, technology roadmaps, customer requirements, and long-term capacity strategies. The Vice President serves as the senior operational leader for Boise manufacturing and is accountable for operational excellence across safety, quality, yield, cycle time, cost, delivery, workforce capability, and capacity utilization. As a member of the Global Front End Operations Leadership Team, the VP partners closely with Technology Development, Engineering, Business Units, Supply Chain, Procurement, Facilities, Quality, Finance, Human Resources, and peer manufacturing sites to drive world-class manufacturing performance and enterprise-wide outcomes. This leader will play a critical role in shaping the future of advanced semiconductor manufacturing through the deployment of next-generation technologies, automation, digital manufacturing capabilities, AI-enabled operations, and large-scale capacity expansions. Key Responsibilities<

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an IT Network Engineer at Micron, you will be responsible for the operational health (Security, Availability, Performance, Interoperability and Reliability) of Micron’s data communications systems. You will support the acquisition, installation, maintenance, and administration of Micron’s data and voice communications systems. Network Engineers specialize in LAN/WAN, Wireless, and Telecommunications hardware, software and cabling. You will regularly work with Micron’s Business Units to ensure solutions meet or exceed business requirements. You will be expected to suggest, promote, and leverage published standards to minimize environment complexity and ensure regulatory as well as license compliance. Responsibility Collaborate with various teams and functional areas in developing and improving business processes with clear and agreed-upon business rules Develop process improvement strategies across the network Prioritize and manage multiple projects based on Department and corporate objectives Lead and collaborate with various engineering groups to optimize current processes and align the network to improve manufacturability, yield, quality and cost performance of products Work with process integration team to implement and integrate new/improved process workflow Maintain documentation for new and improved processes Communicate project strategy, status and actions through meetings, presentations and reports to

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an IT Network Engineer at Micron, you will be responsible for the operational health (Security, Availability, Performance, Interoperability and Reliability) of Micron’s data communications systems. You will support the acquisition, installation, maintenance, and administration of Micron’s data and voice communications systems. Network Engineers specialize in LAN/WAN, Wireless, and Telecommunications hardware, software and cabling. You will regularly work with Micron’s Business Units to ensure solutions meet or exceed business requirements. You will be expected to suggest, promote, and leverage published standards to minimize environment complexity and ensure regulatory as well as license compliance. Responsibility Collaborate with various teams and functional areas in developing and improving business processes with clear and agreed-upon business rules Develop process improvement strategies across the network Prioritize and manage multiple projects based on Department and corporate objectives Lead and collaborate with various engineering groups to optimize current processes and align the network to improve manufacturability, yield, quality and cost performance of products Work with process integration team to implement and integrate new/improved process workflow Maintain documentation for new and improved processes Communicate project strategy, status and actions through meetings, presentations and reports to

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron has an opening for a Photolithography Engineer (Level 2 or 3) at our Boise, Idaho facility. This position is part of Micron’s Technology Development organization, where advanced ideas become manufacturable technologies. Our team works at the leading edge of memory innovation, partnering across design, integration, manufacturing, and equipment suppliers to enable the next generation of semiconductor devices. This is where curiosity, experimentation, and impact come together. As a Photolithography Engineer, you will play a key role in developing and integrating lithography processes that directly shape future memory technologies. You will work hands-on with tools, materials, layouts, and data, while leveraging Artificial Intelligence and other software, collaborating with global partners to move innovations from R&D into high-volume manufacturing. This role offers broad technical exposure and the opportunity to influence device performance, yield, and cost at scale. Responsibilities: Develop and integrate photolithography unit processes for advanced memory technologies Perform material evaluations, reticle, and layout development, OPC, overlay optimization, and process window analysis Drive yield improvement, failure analysis, and device performance optimization Partner with equipment vendors to evaluate tools and improve process capability Document processes, communicate results, and support technology transfer to manufacturing Leverage Artifi

NVIDIA’s Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first-principles thinking and engineering judgment at the highest level translate directly into product outcomes at scale. We are looking for a Principal Performance and Manufacturing Architect who has built the models, defined the specs, and seen them validated through silicon. You have owned the connection between design intent and manufacturing reality, not as a reviewer or a contributor, but as the person who set the methodology and proved it worked. You turn ambiguous physical phenomena into quantified, defensible margin terms. You do not wait for data to confirm your hypothesis; you design the experiment that gets it. You improve how the organization ships products after every program. The exceptional hire also uses AI deliberately — with proven workflow impact and the judgment to know where it compresses real work and where it introduces risk. What you'll be doing: Own the physics, from mechanism to margin. Build first-principles models connecting AVF, defect mechanisms, and DVFS transients to field FIT, system-level yield, and DPPM vs. coverage — calibrated per node and population shift — so every margin term in the V/F curve and P-state table is named, sourced, and defensible. Set the screen that resolves escapes. Specify ATE and SLT voltage, frequency, and timing conditions that capture worst-case transient VF windows — making it unambiguous whether a marginal defect or timing violation is detected or escapes at every manufacturing stage. Make the POR the authoritative source. Author the methodology document for each program and drive alignment across build, product definition, reliability, and test engineering — so every team is making decisions from the same model. Prove the model before produc

As one of the technology industry's most desirable employers, NVIDIA has been redefining accelerated computing, computer graphics and leading the Artificial Intelligence revolution. NVIDIA's innovation is fueled by its great technology—and amazing people. We are seeking a Senior Silicon and System Product Lead to influence, innovate and take our next generation products to the market. As part of the Silicon Solutions Team, we architect and deliver groundbreaking system solutions that integrate all aspects of the system from silicon design, software design to operations and final deployment in multiple market segments that NVIDIA serves. This position offers an unique opportunity to collaborate with multiple organizations in the company and grow your career in a high impact role. We need a passionate, hard-working and creative individual to lead the products all the way from market analysis to delivering the features on the final product. What you'll be doing: Drive product performance and power targets, trade-off features/configurations and provide innovative solutions to complex silicon and system level problems. Evaluate new market segments and use cases; translate market requirements to engineering problem statements and metrics. Innovate Performance, power, yield and quality optimizations and features for the world’s fastest power-shipping products in the GPU and SoC market segments spanning gaming, automotive, datacenter and DL/AI. Develop methodologies and requirements for multi-functional teams to drive silicon and system product features to production. Incorporate productization feedback to improve the next generation. Lead the team for feature requirements and schedule from architecture to silicon phase of projects. Work alongside system architects, designers, marketing teams, chip and board designers, software/firmware engineers, HW/S

NVIDIA's accelerated computing platforms move data at speeds that push the limits of what silicon and physics allow. Whether a high-speed interface trains reliably, maintains accurate margins, and survives every platform topology it will ever see is a question we answer ourselves. This role does that work. The Silicon Co-Design Group leads the boundary between what was designed and what was built. When a GPU, CPU, or SoC ships with interfaces that work at scale, this team is the reason. Most engineers debug within a layer. You will own the full stack. When an interface fails to train, the link margin is unexpectedly tight, or a customer reports a critical silicon issue, you trace the problem through protocol behavior, signal integrity, firmware, platform topology, and silicon marginalities. You then confirm that the fix works. Your methodology shapes how NVIDIA validates high-speed interfaces across generations. Your decisions affect yield, production ramp, and field quality. This is not a coordination role. The engineers who do it well hold protocol depth and system breadth simultaneously, never lose the thread across hardware, firmware, and software, and have the judgment to know when to go deeper and when to act. They are rare. Should that describe you, read on. What you'll be doing: Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness. Close the hardest failures. Drive root cause across protocol behavior, signal integrity, firmware and driver interactions, platform topology, and silicon marginalities and own every fix through to confirmation. Define validation strategy. Set test coverage, debug priorities, margining methodology, and stress criteria f