Analytics Manager in United States

Job Details: Job Description: Join Intel's Advanced Packaging Technology Development - Substrate and Wafer Assembly (ATPD: SWA) team and help us fulfill our mission to be the supplier of choice for leading-edge, cost-effective substrate packaging. As a Manufacturing Equipment Technician, you will support critical manufacturing equipment and drive continuous improvement in a highly technical, cleanroom production environment. Shift 5: Shift 5: (days frontend) AM-PM Sun-Tues and alternating Wednesday days / Hours: 6:00 a.m.-6:00 p.m. Manufacturing Equipment Technicians in Advanced Packaging Technology Development: Substrate and Wafer Assembly are responsible for: Performing electrical and/or mechanical troubleshooting to diagnose issues with non-functioning electromechanical equipment used in semiconductor manufacturing. Dismantling, adjusting, repairing, and assembling equipment according to layout plans, blueprints, operating or repair manuals, rough sketches, or engineering drawings. Performing setup, calibration, and preventive maintenance on production equipment, with a focus on wet chemistry, plating, and dry high-vacuum toolsets. Documenting maintenance activities, repairs, parts usage, and findings in accordance with established procedures and systems. Collaborating with engineering, process, and support teams to improve tool performance, reduce equipment downtime, and enhance process capability and reliability. Leading or contributing to continuous improvement projects, including root cause analysis, yield and uptime improvement initiatives, and optimization of maintenance practices. Assignments are semi-routine in nature and performed within generally defined parameters. Employees normally receive general instructions on most work and are expected to exer

We’re building a world of health around every individual — shaping a more connected, convenient and compassionate health experience. At CVS Health®, you’ll be surrounded by passionate colleagues who care deeply, innovate with purpose, hold ourselves accountable and prioritize safety and quality in everything we do. Join us and be part of something bigger – helping to simplify health care one person, one family and one community at a time. Position Summary Reporting to the Finance Director, this position (Sr Accountant) assists in the preparation of financial statements, journal entries and supporting documentation specifically for Federal Grants and Non-Title funds from the State of AZ. This position’s responsibilities include, but are not limited to, preparing regulatory reports, recording detailed transactions, analyzing variances in the general ledger, and reconciling cash and balance sheet accounts. Incumbent will cross-train to support various accounting and finance functions. Primary Job Duties & Responsibilities: Complete all necessary analysis and research for federal grants and monthly grant invoice review (CER’s) and financial statement reporting, balance sheet reconciliation and journal entries by utilizing Excel, QuickBase, banking information and the Great Plains Accounting System. Complete weekly Research related to provider invoices for grant funding and work closely with the providers for required grant support and reporting. Complete monthly wires for provider payments that require entering the payment into QuickBase including the calculation support for approval. Prepare regulatory reports adhering to all contractual reporting obligations to our regulatory agent on a monthly/quarterly and annual basis per the reporting guide from Mercy Care regulators (AHCC

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Design Technology Co-Optimization (DTCO) team works at the intersection of process technology, standard cell architecture, and design implementation to optimize power, performance, and area (PPA) for advanced memory products. The team collaborates closely with standard cell library, RTL, and physical design engineers to evaluate design tradeoffs and develop methodologies that improve silicon outcomes. As a DTCO Intern, you will gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level. You will use industry-standard place-and-route tools and AI-enabled automation techniques to implement, benchmark, and optimize logic blocks while developing practical skills in physical design, timing closure, and design analysis. Responsibilities Implement standard cell logic blocks using industry-standard physical design tools, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization activities focused on PPA assessment. Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations, identifying opportunities for improvement. Perform static timing analysis (STA), investigate setup and hold timing violations, and support timing closure activities. Execute physical verification checks, including DRC, LVS, and IR-drop analysis, and assist with resolving design issues. Leverage Generative AI, AI Assistants, and Agentic AI solutions to automate data collection, reporting, comparison, and w

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron Technology’s DRAM and Emerging Memory Group (DEG) is a distributed team of engineers and innovators focused on advancing next-generation memory technologies. For more than 43 years, Micron has been a leader in semiconductor innovation, delivering solutions that power applications ranging from artificial intelligence and high-performance computing to immersive digital experiences. The team is committed to innovation, integrity, sustainability, and meaningful community impact while driving the future of memory technology. As an HBM Memory Design Engineer, you will design, analyze, and optimize digital, analog, and memory circuits used in High Bandwidth Memory (HBM) products. You will collaborate with global design, verification, and product teams to develop high-performance DRAM solutions that meet manufacturability, reliability, and performance objectives. This role provides the opportunity to contribute to innovative memory technologies supporting AI, HPC, and data-centric applications. As part of Micron’s AI-Enabled workforce transformation, you will leverage AI-Assisted tools and data-driven methodologies to improve engineering productivity, accelerate design analysis, enhance decision-making, and drive innovation throughout the product development lifecycle. Responsibilities Design, analyze, and optimize memory, logic, and analog circuits for HBM products, including support for layout, validation, and tape-out activities. Perform circuit verification, parasitic modeling, and design simulations

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet ambitious power, performance, area, and schedule targets. You will also work to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic). Collaborate with SoC architects to translate architectural and micro‑architectural specifications into high‑quality RTL implementations. Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure. Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues. Contribute to design documentation, block specifications, and design reviews. Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds. Minimum Qualifications Bachelor’s or master’s degree in electrical engineering, Computer Engin

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. In this position, you will work and support the efforts of groups such as Design Engineering, Product Engineering, Process Integration, Probe, and Assembly to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer happiness. How To Qualify: B.S.EE degree with + 2 years of experience M.S.EE degree with 1+ years of experience. Coursework in CMOS Circuit Design and VLSI Coursework that included crafting the physical layout of circuits Knowledge and experience using Cadence Virtuoso Excellent problem-solving and analytical skills A self-motivated, hard-working team player who enjoys working with others. Good communication and documentation skills Drive innovation into the future Memory generation with a dynamic work environment. What Sets You Apart: Knowledge of layout synthesis and place and route techniques Experience with LVS and DRC tools such as Calibre Utilize AI-Enabled tools to assist in layout floor planning, place and route Standard cell construction and analog layout techniques Having an innovative approach that is open to improving upon any of our processes or products. As a world leader in the semiconductor industry, Micron is dedicated to your persona

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s Advanced Packaging Technology Development (APTD) organization, where new AI assisted packaging technologies are developed to enable future generations of memory and storage solutions. Our team works closely across engineering disciplines to improve manufacturing performance, solve complex technical challenges, and support the technologies driving advances in AI and high-performance computing. As a Shift Process Engineer, you will play a key role in supporting and improving assembly processes within a fast-paced development environment. You will investigate process issues, use data to drive decisions, and work with cross-functional teams to improve yield, quality, and operational performance. This role offers the opportunity to make a direct impact on process capability while collaborating with teams across Micron's global network. Responsibilities: Identify, diagnose, and resolve process issues using failure analysis, FMEA, 8D, SPC, and FDC methodologies Analyze process and manufacturing data to improve yield, product quality, and cost performance

PWI R&D Writing Systems Engineer Description - A Writing Systems Engineer is an experience individual contributor responsible for owning system-level performance of industrial inkjet web presses , with a strong emphasis on hands-on engineering, on-press troubleshooting, and technical leadership . This role leads complex problem solving across ink, printhead, media, firmware, and mechanical systems, driving print quality, reliability, and robustness through a combination of deep systems thinking and direct experimentation . The specialist serves as a key decision-maker in resolving ambiguous, cross-functional issues and ensuring successful product delivery. Responsibilities Hands-on system ownership & advanced troubleshooting (Primary) Serve as the technical owner for system-level performance , including print quality, reliability, and production robustness Lead hands-on troubleshooting on industrial web presses , diagnosing complex print defects (banding, mottle, nozzle behavior, edge effects, etc.) Design and execute on-press experiments (DOEs) to isolate root causes and quantify system sensitivities Drive root cause analysis across subsystems (ink formulation, printhead, firmware, mechanics, media) and implement corrective actions Support press bring-up, ramp, customer escalations, and field issues , often in high-pressure situations requiring rapid, data-driven decisions Translate real-world press behavior into actionable engineering insights and design improvements System design & integration leadership Define and develop system-level solutions to optimize ink/media interactions, printhead performance, and image quality Lead integration of subsystems (ink, printheads, m

We anticipate the application window for this opening will close on - 30 Sep 2026 Careers that change lives start here. Medtronic is a global leader in healthcare technology with a Mission to alleviate pain, restore health, and extend life. Our 95,000 employees work across more than 150 countries to put patients first — developing innovative medical technologies that improve the lives of 72+ million patients each year. Your unique talents will help shape the future of healthcare while building a career grounded in purpose, growth, and impact. A Day in the Life The Brooklyn Center manufacturing site plays a critical role in delivering medical technologies that support patients around the world. As part of the Supply Chain organization, the Production Planning function is responsible for aligning demand, capacity, inventory, and manufacturing execution to ensure operational continuity, support business growth, and enable reliable product availability. At Medtronic, we must work with a sense of purpose and ownership, knowing there is a human life on the other side of every decision. This onsite position is based on-site in Brooklyn Center, Minnesota and partners extensively with Operations, Manufacturing, Engineering, Quality, Finance, Demand Planning, and Commercial teams. The role serves as a key supply chain leader, influencing planning strategies and operational decisions across the manufacturing network. The Principal Production Planner is a strategic supply chain leader responsible for shaping production and capacity planning decisions that drive manufacturing performance, supply continuity, and customer fulfillment. This role combines data-driven analysis, systems expertise, and cross-functional leadership to develop planning strategies, optimize resource utilization, mitigate supply

What we’re doing isn’t easy, but nothing worth doing ever is. Diligent builds helpful robots that work safely and autonomously in real world environments. We move quickly, solve messy problems, and care deeply about reliability at scale. We’re hiring a Manufacturing Reliability Engineer to own production test for our robots at our contract manufacturer: you’ll design and run robust end-to-end test protocols, provision fleets of robots for production, and own the KPIs that define production quality. This role is based in Austin, TX. However, the position will require 50% travel to the Milwaukee, WI area and requires close collaboration across software, hardware, operations, and product engineering teams. Key Responsibilities End-to-end test process ownership. Create, validate, and maintain production test protocols and gating criteria from incoming inspection through final test and shipment. Provisioning of bots. Design and operate provisioning flows (imaging, firmware deployment, configuration, validation) and the tooling/fixtures needed to provision and handoff robots for production. KPIs and continuous improvement. Own key production metrics — First Pass Yield (FPY), cycle time, and test coverage — and drive continuous improvements to meet throughput and quality targets. Test automation & infrastructure. Architect, implement, and maintain automated test frameworks, harnesses, and test rigs used at the CM site. Ensure tests are stable, fast, and provide actionable failure data. Cross-functional escalation & RCA. Lead root-cause analysis for field and production failures; coordinate corrective actions with design, firmware, and CM engineering to close quality loops. On-site production leadership. Be the onsite technical authority at the contract manufacturer: train operators, debug failures on the line, and continuously refine processes with CM partners. What Success Looks Like Improved FPY and reduced rework rates across production builds. Reduced per

We take play seriously. We’re looking for curious adventurers ready to find their party, fueled by imagination and drive to build what’s never been built before. At Hasbro and Wizards of the Coast, you’ll collaborate with passionate teams to reimagine our iconic brands and create experiences that spark joy, connection, and community through the magic of play. This is your chance to shape legendary play that lasts a lifetime. The Senior Network Engineer leads Wizards of the Coast's enterprise network — datacenters, corporate offices, studios, and AWS cloud. Our stack runs on a Juniper/Mist campus fabric, a Palo Alto Networks security edge, and cloud-native AWS connectivity. You'll set technical direction, drive complex initiatives end to end, and mentor the broader team. Come help us build the future of network operations. What You'll Do: Own the architecture, build, and roadmap for our Juniper/Mist campus and branch infrastructure, and lead its evolution across sites and business units. Lead the Palo Alto Networks security stack, from policy architecture to secure-by-design standards across teams. Own end-to-end AWS cloud network implementation — VPC, Transit Gateway, Direct Connect/VPN, Route 53 — and hybrid connectivity, including BGP, OSPF, and SD-WAN traffic engineering at scale. Drive automation and AI adoption across network operations, from config deployment to AI-powered monitoring, observability, and root-cause analysis. Be the go-to for critical issues, and mentor less-experienced engineers through code review, troubleshooting, and skill-building. What You'll Bring: 10+ years in enterprise network engineering — routing, switching, wireless — with deep expertise in Juniper (EX/QFX/SRX, Mist) and/or Cisco (Catalyst, Nexus), plus hands-on work with intelligent ops tools like Mist/Marvis at scale. Expert-level BGP, OSPF, SD-WAN, and load balancing chops. You've built these solutions from scratch, not just maintained them! Extensive Palo Alto Net

Strength in Trust OneTrust’s mission is to enable innovation through the responsible use of data and AI. We believe that ensuring data is trusted shouldn’t slow teams down—it should accelerate what’s possible. This led us to develop the first technology platform for responsible data use in 2016. Today, with AI representing the latest and most impactful expansion of data yet, OneTrust is once again redefining what responsible innovation looks like. OneTrust, the AI‑Ready Governance Platform™, unifies regulatory intelligence, automation, and connected governance workflows so businesses can continue to move at the speed of AI while ensuring good governance to prevent data misuse at scale. Trusted by thousands of organizations worldwide, OneTrust is shaping the future where trusted data becomes a transformative force for business and society. The Challenge As a Senior Renewals Associate, you are a strategic driver of customer retention and revenue predictability. You bring rigor to every renewal conversation – leading with insight, ensuring precision in forecasting, and removing friction in the renewal lifecycle. You act as a trusted advisor to internal partners and customer stakeholders alike. Your Mission Lead renewal strategy across a complex portfolio of high-value accounts within the Commercial Business Unit. Deliver exceptional accuracy in renewal forecasting through deep analysis, historical trends, and direct engagement insights. Identify early warning signs of churn or contraction and implement mitigation plans in collaboration with Customer Success and Sales. Own renewal negotiations with executive-level stakeholders, advocating for value while protecting revenue. Partner with Revenue Operations and Finance to enhance renewal workflows, documentation, and reporting frameworks. Mentor and support junior team members through deal coaching and renewal planning. Provide input to leadership on process improvements, renewal playbooks, and enablement ini

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to define and implement RTL for high-performance CPUs. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in CPU microarchitecture with expertise in Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache or Datapath. Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis. Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments. Background in microarchitecture definition, design specification, and performance-driven trade-off analysis. What We Need Own RTL design and microarchitecture development for a portion of a CPU block of a high-performance RISC-V CPU. Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals. Use innovative techniques to optimize power, performance, and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team and lead the front-end RTL physical implementation team. Drive CAD flows on multiple process technologies while working closely with core micro-architects to refine CPU core configurations and optimizing PPA. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, RTL and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An expert in physical design practices used to optimize PPA Experienced in high-performance physical design. Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis. Skilled in synthesis, place and route tools including flows and physical design methodology. Background in CPU micro-architecture. What We Need Own front‑end physical implementation and PPA definition for a high‑performance RISC‑V CPU and CPU subsystem Work closely with microarchitects and RTL designers to “make the IP better” by optimizing frequency, power, and area

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers. You will own CPU core-level testbench development and verification, shaping how our out-of-order RISC-V CPUs behave in silicon. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU verification, CPU testbench development, or closely related digital design. You have deep hands-on experience building and owning CPU core-level testbenches, not just using existing environments. You know high-performance out-of-order CPU microarchitecture in depth. You are comfortable developing testbench infrastructure in CVM methodology, with UVM experience as a strong plus. You work comfortably across RTL, waveforms, logs, regressions, and cross-functional debug with design, DV, emulation, and post-silicon teams. You are comfortable using AI-assisted verification workflows to improve debug, stimulus creation, and coverage analysis, while applying strong engineering judgment to validate results. What We Need Lead hands-on CPU core-level testbench development for hi