High Speed Ai Interconnect Signal Integrity Engineer in United States

NVIDIA is a global leader in high-speed computer vision, artificial intelligence (AI), and deep learning. Our team develops data engineering solutions that empower AI developers in autonomous vehicle (AV) domains to innovate quickly and effectively at scale. Are you ready to take on a senior technical role in building high-performance AI data pipelines? We seek an exceptional individual to design and optimize microservices and data pipelines to process massive volumes of AV data and enable seamless data mining and AI training. The ideal candidate will bring expertise in big data processing and distributed computing to create efficient solutions and overarching architectures for challenges such as video data curation, behavioral search, and AI dataset management. What you'll be doing: Scope and build tools, microservices, workflows, and distributed applications to accelerate data mining and AI training. Design and implement solutions for streaming, resilience, logging, security, authentication, workflow orchestration, and data management. Deploy AI models. Design and develop Retrieval-Augmented Generation (RAG) workflows enabling hybrid and agentic patterns. Analyze and operationalize complex distributed systems for speed-of-light performance. What we need to see: Experience developing high-performance, scalable software systems. MS with 6+ years, or BS (or equivalent experience) with 8+ years of relevant experience in Computer Science, Computer Engineering, or a related technical field. Strong programming skills in Python or Golang Proficiency in key technologies like Kubernetes, Helm, Hive, Parquet, SQL, vector databases, e.g., Milvus. Strong architectural skills with a proactive, problem-solving mentality. Experience in data mi

NVIDIA's accelerated computing platforms move data at speeds that push the limits of what silicon and physics allow. Whether a high-speed interface trains reliably, maintains accurate margins, and survives every platform topology it will ever see is a question we answer ourselves. This role does that work. The Silicon Co-Design Group leads the boundary between what was designed and what was built. When a GPU, CPU, or SoC ships with interfaces that work at scale, this team is the reason. Most engineers debug within a layer. You will own the full stack. When an interface fails to train, the link margin is unexpectedly tight, or a customer reports a critical silicon issue, you trace the problem through protocol behavior, signal integrity, firmware, platform topology, and silicon marginalities. You then confirm that the fix works. Your methodology shapes how NVIDIA validates high-speed interfaces across generations. Your decisions affect yield, production ramp, and field quality. This is not a coordination role. The engineers who do it well hold protocol depth and system breadth simultaneously, never lose the thread across hardware, firmware, and software, and have the judgment to know when to go deeper and when to act. They are rare. Should that describe you, read on. What you'll be doing: Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness. Close the hardest failures. Drive root cause across protocol behavior, signal integrity, firmware and driver interactions, platform topology, and silicon marginalities and own every fix through to confirmation. Define validation strategy. Set test coverage, debug priorities, margining methodology, and stress criteria f

About Dawn Aerospace Dawn Aerospace is redefining space transportation through reusable, sustainable, and high-cadence flight systems. Our Aurora Spaceplane enables rapid access to suborbital space and speeds over Mach 3, serving a growing need for near-space testing, high-speed flight, and microgravity research. Together with our in-space propulsion business, Dawn is building the infrastructure for sustainable access to and operation in space. Role Overview Aurora is the first vehicle capable of flying missions to the edge of space multiple times a day. Your job is to transform this vehicle capability into mission success for our customers working from anywhere in the US - although Huntsville , USA is preferred (with domestic and international travel) . As a Mission Manager, your core role is to translate customer objectives into executable flight plans. You will be the customer’s interface to Dawn's flight operations, engineering, regulatory, and commercial teams. Throughout any project, you will coordinate the specialists required to solve individual problems while retaining responsibility for the mission. This is not a passive account-management role. You will be expected to assess mission feasibility, challenge customer assumptions, defend engineering realities, and drive clarity across complex, first-of-a-kind mission concepts. You will be the customer’s technical advocate inside Dawn, and Dawn’s operational interface to the customer. You will succeed here if you can lead through ambiguity, communicate with precision, and have the technical depth to engage meaningfully with aerospace engineers and flight operators, while keeping customers aligned, informed, and confident. Key Responsibilities Mission Ownershi

We are now looking for a Senior SRAM Engineer within our Full Custom Memory (FCM) team! The FCM team designs specialized RAM implementations across NVIDIAs wide array of processing chips. Be it high speed, low power, multiport, we engage closely with processor architecture teams to build custom solutions across the entire NVIDIA silicon portfolio. Are you interested in designing circuits for the next generation of AI chips? Join a team of dedicated engineers developing the custom SRAM circuits that help power these chips. What you'll be doing: Design best-in-class SRAM circuits using state-of-the-art technology processes Optimize circuits for performance, area, and power Collaborate with mask designers to craft high quality and dense pitch-matched layout Verify functionality, electrical integrity, and robustness Improve/develop flows and methodologies to streamline design automation, data collection, and analysis to ensure working silicon What we need to see: BS/MS/PhD (or equivalent experience) in Electrical or Computer Engineering Minimum 12 years of circuit design experience Strong understanding of SRAM and memory design techniques and macro/block development Ways to stand out from the crowd: Self-motivation, attention to detail, clear data analysis and presentation skills Familiarity with industry tools such as Cadence Virtuoso for schematic and layout, SPICE simulators, waveform viewers Background with developing and using various flows and methodologies, in

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for the most advanced AI/HPC silicon and package design. This role focuses on high-speed SerDes and memory channel architecture, advanced 2.5D/3D package SI/PI, substrate to package co-design, power-delivery-network optimization, electromagnetic modeling, and simulation-to-measurement correlation. The ideal candidate has strong hands-on experience with high-speed channel and PDN analysis across ASIC packages, interposers, substrates, and power-delivery structures, and can translate simulation results into practical design requirements for interposers and package substrate design optimization. The engineer will work closely with ASIC, package, system, mechanical, thermal, power, and silicon validation teams from early architecture and feasibility studies through production bring-up. In this role you will Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility studies through production. Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces. Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers. Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps based on SI/PI re

NVIDIA's GPUs and SOCs are the world leaders in power, performance and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in the world through their contributions! This position will collaborate with Technical Package Lead and different design teams in the design and development of sophisticated, detailed layout of IC substrates for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues. What you'll be doing: As part of a Layout team, you will collaborate to implement high speed/density ASIC packages. Perform substrate breakout patterns for ASIC packages. Optimize package pinout incorporating system level trade-offs of pins assignment. Help perform package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite. Propose layout design trade-offs to the Technical Package Lead for resolution and implementation. Conduct design feasibility studies to evaluate the Package design goals for size, cost, and system performance. Develop symbols and CAD library databases using Cadence APD design tools Develop methodologies to improve layout productivity What we need to see: Hold a B.S. Electrical Engineering or equivalent experience 5+ years experience in PCB Layout of graphics cards, motherboards, line cards or other related technology. Experience with HDI designs is a plus Proven experience in substrate layout of wire bond and flip chip packages, preferred Significant background with Cadence AP

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our team is at the forefront of developing next-generation memory and AI computing platforms. We are core contributors to the design, validation, and mass production of advanced systems using emerging memory technologies, ASICs, FPGAs, high-speed digital interfaces, mixed-signal and analog circuitry, and complex power delivery architectures! We are seeking a highly experienced Mechanical & Thermal Engineer to provide technical leadership and drive the mechanical and thermal architecture of ground breaking hardware platforms. This role offers the opportunity to influence product strategy, lead critical engineering decisions, and collaborate across global multidisciplinary teams to enable world-class computing solutions. The ideal candidate brings deep expertise in thermal, mechanical, and heat mitigation solutions for memory product. They demonstrate strong analytical and problem-solving skills. They have a proven record of delivering products from concept through high-volume manufacturing! Performs design and development engineering assignments related to hardware products and systems including development of new products or updates to existing products. Work may encompass one or more areas of engineering including electronic design, mechanical design, or other related fields. Duties may include research, evaluation, development, and application of new processes and methods into products. May be responsible for establishing and conducting testing routines, developing or implementing project plans, budgets, and schedules, and documentation

NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems Engineer at NVIDIA, you'll join a group of hardworking engineers to develop and architect innovative Memory Solution for Tegra SoCs. In this position, you'll make a real impact in a multifaceted, technology-focused company. You will work with memory controller/PHY and Platform / System architect, Firmware, SI/PI, Memory suppliers to design and architect cutting edge, high speed and lower power memory technology for NVIDIA CPUs and SOCs. What You Will Be Doing: Analyze future DDR/LPDDR/HBM technologies to determine optimum performance, power, function and RAS in memory for Next generation SOC and Systems. Collaborate with ASIC Architects, Designers, Software and Firmware SW/FW teams to drive memory technology and associated requirements for memory controllers. Define Memory module, Package, and PCB layouts appropriate to the system workloads Debug and bring up memory evaluation / validation and failure issues on memory technology. Collaborate with DRAM suppliers and industry partners on to develop memory and memory related component technology. What We need to see: Bachelor's degree or master’s degree in Electrical Engineering, Computer Engineering (CE), or a related field (or equivalent experience) 10 years of proven track record in DRAM design, module design, or memory sub system design. Deep understanding and strong fundamental of memory design, features, ECC algorithm, SI and PI (Training algorithm) in DDR, LPDDR, and HBM. Strong understanding of memory sub system level interaction with Cache, Memory controller and PHY. Experience in the design, bring-up and validation for memory failure analysis Experience with Python, C/C

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. NVIDIA’s Silicon Co-Design Group is hiring a Chip Lead to serve as the technical lead for one of our most consequential silicon programs! This is not project management, and it is not a senior IC role. You are the person the program partners with on its hardest technical questions — when the right answer is not obvious, and when leadership needs a single technical perspective to align on direction. You are accountable for the technical integrity of the chip end-to-end. You guide co-design feature integration, help resolve the toughest multi-functional bugs, and serve as the project-specific custodian of the qualification playbook. The program runs cleaner because you are on it! What you’ll be doing: You will partner across design, validation, software, and manufacturing to keep the program’s technical narrative clear and on track. Day to day, you will: Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs. Co-lead program-level feature integration from chip to system, surfacing inter-function dependencies and guiding them to resolution. Help resolve the program’s hardest multi-functional bugs by translating ambiguous, multi-team symptoms into root-cause closure on areas such as HBM, power and thermal, high-speed I/O, and packaging. Steward the qualification playbook. When the playbook does not fit a situation, guide the mitigations and capture the lessons as reusable methodology for other SSG programs. Shape the program’s technical narrative by surfacing key risks, trade

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Curious about how cutting-edge hardware actually comes to life? We're looking for someone who’s excited to dive into the core of next-gen systems and help make them real. In this role, you’ll validate high-speed interfaces, solve complex system-level puzzles, and collaborate across teams to shape the future of AI/ML computing. If firmware, hardware, and hands-on debugging sound like your kind of fun — let’s chat! This role is hybrid and based in Vancouver, Canada. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You love bringing hardware to life and enjoy the thrill of solving tricky problems across the hardware–firmware boundary. You’re hands-on in the lab and comfortable with tools like oscilloscopes, protocol analyzers, and JTAG — digging deep doesn’t scare you. You’re comfortable jumping into unfamiliar problems and figuring things out — whether it’s in the lab or in firmware. You’re curious, collaborative, and excited to work on technology that pushes the boundaries of performance. What We Need Someone to take the lead in validating our next-gen PCIe interfaces — from controller to PHY, and everything in between. A strong co

About the Team Our Robotics team is focused on unlocking general-purpose robotics and advancing toward AGI-level intelligence in dynamic, real-world environments. Working across the full model and systems stack, we integrate cutting-edge hardware and software to explore a broad range of robotic form factors. We strive to seamlessly blend high-level AI capabilities with the physical constraints of real-world systems to improve people’s lives. About the Role We are looking for a PCB Layout Engineer to design high-density electronics for next-generation robotic systems. You will own PCB layout from floor planning through fabrication release, working closely with electrical, SI/PI, mechanical, and manufacturing teams. This role is based in San Francisco and requires in-person presence four days per week. In this role, you will: Own PCB layout, component placement, routing, and fabrication release for complex robotic systems. Collaborate with SI/PI engineers to refine layouts based on simulation results. Implement high-speed routing, controlled impedance, power distribution, decoupling, grounding, EMI/EMC, thermal, and mechanical-integration requirements. Work directly with fabricators and assembly partners to define stack-ups, establish design rules, drive DFM/DFA/DFT reviews, and close findings before release. Prepare fabrication and assembly documentation, including drawings, ODB++, drill files, stack-up tables, and manufacturing notes. Inspect newly received PCBAs and participate in board-level manufacturing failure analysis. Contribute to reusable design constraints and layout workflows, and maintain component-library assets such as symbols, footprints, and 3D models. You might thrive in this role if you: Have 6+ years of experience designing complex, multilayer PCBs. Are fluent in Cadence Allegro PCB Designer and Constraint Manager. Have strong HDI design experience, including fine-pitch BGAs, microvias, blind and buried vias, via-in-pad, and sequential lamination.

What you’ll do Act as the in-house electrical lead for Midjourney Medical: own the electrical architecture of the scanner and the technical direction for all board-level design. Own complex board design end-to-end: architecture, schematic capture, layout (high-speed digital, analog/mixed-signal, power), DFM/DFT, fabrication and assembly vendor management, bring-up, and revision control. Write firmware for embedded targets (MCU/SoC): drivers, real-time control loops, safety-relevant logic, bootloaders, and field update paths. Audit and update HDL (FPGA) code for high-throughput data acquisition, timing/synchronization, triggering, and pre-processing of ultrasound and sensor data streams. Define electrical interfaces and data contracts with software, recon/ML and mechanical teams: timing budgets, clocking/sync, signal integrity, connectors/harnessing, and failure modes. Establish electrical engineering rigor: design reviews, schematic/layout review checklists, bring-up procedures, test fixtures, and documentation suitable for a regulated medical device program (DHF, traceability, change control). Mentor and grow the electrical function; select and manage external design partners where leverage is high. What we’re looking for Deep experience designing complex boards from blank page to stable revision, including high-speed digital and analog/mixed-signal domains. Strong schematic and layout skills (Altium/KiCad or equivalent) with real signal integrity, power integrity, grounding, and EMI/EMC instincts. Solid embedded firmware background in C/C++ (and Python for tooling): peripherals, DMA, interrupts, real-time constraints, and debugging on hardware. Practical HDL experience (VHDL/Verilog/SystemVerilog) for data acquisition, timing, and streaming interfaces. Track record of owning bring-up and debug on real hardware: scopes, logic analyzers, and disciplined root-cause analysis. Technical leadership: clear trade-offs, strong written documentation, and the ability to set

About the job Lead the team that proves our AI silicon performs reliably before it reaches customers. You will build and lead Graphcore's characterisation capability for next generation silicon and system platforms. Your work will help ensure our products perform consistently across real world conditions. You will define bring up and characterisation strategies, lead technical execution, and shape the lab infrastructure needed for success. You'll work across silicon, hardware, manufacturing, architecture and product teams to solve complex engineering challenges. This is a hands on leadership role with the opportunity to influence both product design and how Graphcore validates future AI systems. The team and culture This is a newly formed team within Manufacturing Operations. You'll have the opportunity to establish how the team works while building strong partnerships across engineering and operations. Day to day, you'll work closely with architecture, silicon, hardware, production test and product teams. Decisions are driven by data, technical evidence and close collaboration across disciplines. We value ownership and clear communication. You'll be trusted to lead technical direction, remove blockers and help teams make progress with confidence. What we're looking for Essential Proven track record of delivering complex technical projects as an individual contributor, manager, or project manager, with the ability to work independently and drive execution. Strong expertise in silicon digital device design, bring-up, characterisation, and silicon process technologies, with an understanding of their impact on transistor- and system-level performance. In-depth knowledge of high-performance processors, system-on-chip (SoC) architectures, and high-speed digital interfaces such as PCIe, Ethernet, and DDR. Experience with measurement automation, data analysis, and scripting/coding to develop automated test and analysis workflows, with familiarity of ATE systems and t

What you’ll do Be the generalist EE for the scanner system: integration, bring-up, debugging, and making the electrical side of the device reliable and serviceable. Own ultrasound experimentations that feeds the image reconstruction team Design and execute experiment setups for transducer characterization (element sensitivity, bandwidth, cross-talk mapping, beam profile measurements) and ex vivo / phantom clinical testing. Acquire, process, and analyze RF and baseband signals for data quality assessment and benchmarking. Design simple boards and adapters as needed (monitoring, power/safety, interface/conditioning), and take them from prototype through a stable revision. Prototype quickly, then harden what works: wiring/harnessing, grounding, safety interlocks, and reliable integration across subsystems. Own practical test setups and documentation (fixtures, scripts, procedures) that make experiments repeatable and results comparable over time. What we’re looking for Strong hands-on EE background with experience building, debugging, and iterating on real systems in the lab. Solid understanding of signal processing fundamentals — knows what to measure, how to condition and digitize it, and how to evaluate signal quality in the context of an imaging system (SNR, bandwidth, dynamic range, artifacts). Comfortable spanning system integration + occasional design work (schematics/layout reviews or light PCB design) in a fast-moving environment. Ability to work at the boundary between hardware and algorithms: measure reality, communicate constraints, and help close gaps vs simulation. High agency and practicality: able to set up experiments, get trustworthy data, and unblock others on a lean team. Useful experience Analog/mixed-signal, or high-speed data capture experience; strong instincts for instrumentation and noise/debugging. Ultrasound or acoustic sensor handling: hydrophone calibration and field mapping, transducer impedance characterization, element-level sensitivity

About Graphcore Graphcore is a global leader in artificial intelligence computing systems. We design advanced semiconductors and data center hardware that provide the specialized processing power needed to advance AI while improving the efficiency required for broad adoption. As part of SoftBank Group, Graphcore belongs to a family of companies developing transformative technologies. Our AI Engineering Campus in Austin plays an important role in building the hardware platforms that support the next generation of AI systems. The Opportunity As a Systems Engineering Intern, you will contribute to projects that combine hardware, firmware, and software engineering for advanced AI compute platforms. You will work with experienced engineers on subsystem design, laboratory testing, system validation, automation, and performance analysis. The internship provides hands-on experience with modern hardware development and system-level engineering. You will own clearly defined technical tasks with guidance from the team and document your methods, results, and conclusions. What You Will Do Support the design and testing of CPU and high-speed input and output subsystems for advanced compute platforms. Run laboratory tests and measurements to help evaluate performance, power, signal behavior, and reliability. Contribute to system-level validation by creating scripts and tools that streamline testing, data collection, and analysis. Explore emerging input and output technologies, including PCIe 6.0 and 800G Ethernet, and learn how they support advanced computing workloads. Assist with investigations into platform power, cooling, and energy efficiency, including liquid-cooling systems for high-performance processors. Use power meters, oscilloscopes, logic analyzers, or comparable lab equipment under appropriate supervision. Analyze test results, identify unexpected behavior, and work with engineers to reproduce and investigate issues. Collaborate across hardware, firmware, software, m