Lead Solutions Architect in United States

Power and Performance Validation Engineer About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations. This role requires strong technical expertise and collaboration across multiple engineering disciplines to deliver robust validation methodologies, scalable automation frameworks and actionable performance insights. The Team The Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems. The team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debug compl

Staff -Power and Performance Validation Engineer About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations. This role requires strong technical expertise and collaboration across multiple engineering disciplines to deliver robust validation methodologies, scalable automation frameworks and actionable performance insights. The Team The Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems. The team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debu

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about driving innovation for next-generation memory solutions powering AI/ML and high-performance computing systems. As a Director of HBM RTL Design and Integration, you will lead a team responsible for the design, integration, and delivery of next-generation HBM SoC logic die, with a strong focus on RTL development and IP integration. You will drive technical strategy and execution across multiple product generations, working closely with architecture, verification, physical design, firmware, and product engineering teams. Key Responsibilities Lead SoC RTL design and integration for HBM logic die, including subsystem partitioning, IP integration, and SoC-level design convergence. Drive translation of architectural and micro-architectural specifications into robust, high-quality RTL implementations across multiple teams. Oversee SoC integration aspects, including clocking, reset, power intent, configuration infrastructure, and system-level design correctness. Establish design methodologies and best practices to improve quality, reuse, and development efficiency across HBM programs. Partner with SoC Architecture, Verification, Physical Design, Firmware, and System teams to ensure successful end-to-end product execution. Work closely with Product Engineering, Test, Probe, Process Integration, Assembly, and Manufacturing to ensure robust, manufacturable HBM

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will work on the systems software strategy and execution that brings new AI silicon from first power-on to a fully integrated system running production-representative models at expected functionality and performance. You will define how software exercises and validates compute, memory, interconnect, and I/O subsystems, then build the diagnostics, automation, and observability needed to find issues quickly. This role sits at the center of silicon, firmware, platform, systems, and workload teams. You will turn hardware specifications and performance targets into an end-to-end bringup plan, drive cross-functional debug, and establish the stress and regression infrastructure that makes each new platform reliable across operating environments. In this role, you will: Contribute to the end-to-end software bringup and validation strategy for new silicon and first-party systems. Define software-driven test coverage across compute, memory, interconnect, I/O, and their system-level interactions. Build diagnostics, test automation, telemetry, and regression infrastructure that accelerate first-silicon learning and issue isolation. Lead bringup from initial silicon arrival through board and system integration, docking, runtime enablement, and model execution. Design stress tests that characterize reliability, performance, and stability across workloads and operating conditions. Translate architecture specifications and performance models into measurable acceptance crit

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Customer Engineering organization serves as the primary technical interface for our global customers and helps ensure that Micron solutions are seamlessly integrated into next-generation technology platforms. Our team coordinates deep engineering engagements, technical product qualifications, and architecture reviews to secure design wins and grow market share. We are dedicated to providing world-class technical support that accelerates revenue and builds long-term strategic partnerships with our customers. Role Description: The Field Applications Engineer - Associate plays a vital role in achieving the technical achievements needed to launch products. You will be an important member of our field engineering team. In this position, you will oversee many end-to-end technical tasks, including sophisticated product sample deployments, lifecycle management, addressing technical questions, and other customer interactions. You should adopt an "automation-first" approach to actively find ways to improve processes and apply AI-based workflows in daily operations when possible. This role can lead to a full-time FAE career for individuals who achieve the right results. It also requires demonstrating the right skills and behaviors. Example Responsibilities: Coordinate the entire process of tech

Job Details: Job Description: Join Intel as a Module Development Engineer, where you will play a critical role in driving technology development and enabling advanced manufacturing solutions. In this position, you will lead the design and optimization of complex manufacturing processes, including material selection and equipment development, to enable innovative product designs and high-volume production. Your work will directly impact Intel's ability to maintain its leadership in cutting-edge semiconductor technologies. Business group As part of Intel Foundry, you will join a dynamic team focused on advancing semiconductor manufacturing technologies and capabilities. The group's mission includes enabling high-volume production through innovative process integration, equipment solutions, and technology advancements. Collaborating across Intel's global network, you will contribute to driving Intel's success in delivering transformative technologies to its customers. Key Responsibilities Lead the development of manufacturing processes that include MHS equipment development, parameter optimization, and equipment metrology. Perform pathfinding activities to enable emerging device architectures and support process and hardware development. Develop roadmaps for future technologies that align with Intel's leadership in semiconductor innovation. Collaborate with equipment and materials suppliers to implement solutions that meet manufacturing and technology needs. Recommend and execute modifications to equipment and processes to improve efficiency and optimize production output. Stay informed about industry trends in materials and manufacturing processes, identifying opportunities for innovation. Behavioral Traits Strong p

Job Requisition ID # 26WD101260 L'affichage de poste en français suivra / The French job posting follows. 26WD101260, Senior Manager, Product Position Overview Autodesk's Technical Advisory organization helps the world's leading architecture, engineering, construction, manufacturing, and media companies get the most from their Autodesk investments. We are transforming this expertise from traditional consulting into a digital-first platform strategy — and the Senior Manager, Product Management will define what that platform becomes. Reporting to the Director of Platform & Productization within Global Delivery & Solutions, you will lead a product management team responsible for Autodesk's digital consulting platform. Your portfolio spans platform capabilities, industry-specific solutions, consulting tools, and packaged services. In the first year, you will launch and land our first digital consulting offering, validating our new consulting model with paying customers. You will establish product management discipline for a maturing capability — discovery practices, prioritization frameworks, go-to-market coordination — while simultaneously delivering product that proves the model works. You own the product strategy and roadmap. You will partner with Content & Knowledge on knowledge readiness and publication decisions, with Architecture and Engineering on technical feasibility and delivery sequencing, and with GTM on market positioning and launch execution. The role sits at the center of the organization, and yo

Product Manager Enterprise Integrations Description - Role Summary We are looking for a Principal Product Manager to lead the evolution of HP’s Enterprise Integration strategy—from fragmented, point-to-point integrations to a scalable, productized API ecosystem. This role will define and drive a shift toward API-as-a-product, enabling reusable business capabilities, accelerating developer productivity, and laying the foundation for an AI-first, composable enterprise. You will play a pivotal role in transforming our integration landscape into a unified Integration Fabric, and ultimately an Intelligence Fabric that powers next-generation digital and AI-driven experiences. What You’ll Own API Productization Strategy Transform APIs from point solutions into reusable, discoverable product offerings Define capability-based packaging aligned to business domains (B2C, B2B, Partner ecosystems) Drive standardization across design, classification, and maturity frameworks Enterprise Integration Fabric Define integration patterns that unify platform, SaaS, and custom-built APIs Establish a holistic, cross-application view of enterprise APIs Reduce point-to-point integrations through reusable architecture patterns and services Data + API Convergence Partner with Data teams to define and expose data products via APIs Enable consistent access to enterprise data through standardized interfaces Align API strategy with enterprise data governance and cataloging AI-First APIs & Developer Experience Define APIs optimized for AI agents, automation, and developer productivity Build APIs that are discoverable, composable, and machine-consumable Enable next-gen use cases including agent or

Job Details: Job Description: Note: This role requires regular onsite presence to perform essential job responsibilities. This position drives technology development and enablement for both high-volume manufacturing and future process technologies. Responsibilities include providing process integration and equipment solutions, conducting feasibility studies to meet device performance requirements, and leading the design and development of advanced manufacturing processes. The role involves material selection, parameter optimization, metrology, equipment engineering, and system design to enable new product architectures and functional requirements. The successful candidate will lead pathfinding activities that support process and hardware development for next-generation manufacturing technologies and will contribute to technology roadmaps that enable future product innovation. The role also includes identifying and implementing equipment and process improvements to enhance manufacturing efficiency, optimize production output, and improve operational performance. Qualifications: Minimum Qualifications Master's degree in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science, or a related STEM field, with 6+ years of semiconductor industry experience , primarily in dry etch process development. Bachelor's degree in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science, or a related STEM field, with 9+ years of semiconductor industry experience , primarily in dry etch process development. 3+ years of experience collaborating with equipment suppliers (e.g., Lam Research, TEL, Applied Materials, Hit

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Advanced Packaging Technology Development (APTD) team at Micron is shaping the future of memory and storage technologies that fuel the AI era. We collaborate with global R&D groups, suppliers, and manufacturing teams to turn bold ideas into production-ready solutions. We innovate fast, learn continuously, and work as one team! This position is intended to be part of Micron's Technical Leadership Program (TLP). This is a career path for individuals seeking to advance as technical leaders and industry innovators. TLP members are expected to influence, lead, and mentor others. Position Overview: We are seeking an experienced organizational leader who will l ead and influence methodology improvements, including best practices in process development, data-driven decision-making, and application of AI/advanced analytics to drive innovation. In this role, you will drive strategic process development for Micron’s most advanced memory products, including HBM, 3DS DRAM, and emerging 3D architectures. You will guide end‑to‑end technology execution, partner across organizations, and influence both internal roadmaps and the external ecosystem. This is a high-impact role for someone who thrives at the intersection of innovation, complexity, and collaboration. Responsibilities: Own advanced packaging process technologies across wafer‑level and die‑level modules from pathfinding through manufacturing readiness Develop

Senior Java Software Engineer – Developer Company: The Boeing Company The Boeing Company is looking for a Senior Java Software Engineer – Developer to join the Advanced Ground Architecture team located in Herndon, Virginia, Seal Beach, California, El Segundo, California or Colorado Springs, Colorado . This position will focus on supporting the Boeing Defense, Space & Security (BDS) Software Engineering organization. The Advanced Ground Architecture (AGA) software team is dynamic group of software engineers creating the future of Ground support with the extensibility and adaptability to be used across ALL Boeing programs. The software team is executing this vision through modern software technologies (Java, ReactJS, python, CI/CD pipelines) and methodologies (Scaled Agile). AGA is looking for self-motivated high performers to lead and execute the large scope of Java development needed for the program's vision. The ideal candidates will provide software engineering functions for the design, development, and maintenance of complex, multi-tiered application software systems used to support the command and control of space vehicles. The software engineers will work day-to-day with system and test engineers to implement, test, and document new features and improvements for both web services and applications supporting distributed computing solutions. Position Responsibilities: Develops software in conjunction with agile team leadership including participation at agile events Assists in the execution of DevSecOps processes to deliver software baseline on sprint boundaries. Participates in PI planning as an agile team member Engages with users and other engineers

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an Physical Design Engineer to lead cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities. This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are BS in Electrical or Computer Engineering (or equivalent experience) with 5+ years in Physical Design CAD methodology at advanced nodes. Proven track record improving PPA and/or runtime on high-performance, low-power taped-out designs. Hands-on with industry-standard EDA tools (e.g., Fusion Compiler) across synthesis, P&R, STA, signoff, and hierarchical flows. Strong Python/Tcl and data skills, with interest or experience in ML frameworks (PyTorch, TensorFlow), and the ability to drive complex projects independent

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to lead pre-silicon verification of the Beowulf SoC, with focus on the Compute Subsystem (CSS), DDR memory subsystem, and Fabric NoC. This role will drive coverage, coherency, memory traffic, connectivity, error handling, and bring-up features critical to silicon success. This role is hybrid, based out of Boston, MA; Toronto, ON; or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Deeply curious about SoC architecture, compute systems, DDR behavior, and Fabric NoC/interconnect verification. Expert in UVM, SystemVerilog, coverage-driven verification, assertions, and subsystem-level debug. Experienced in verifying compute subsystems, DDR controllers and PHY-facing logic, NoC/interconnect protocols, coherency, ordering, and data movement. Comfortable with reset, power management, error handling, performance, and high-concurrency system scenarios. Proactive, detail-oriented, and effective in cross-functional technical discussions. Familiar with Python, C/C++, Tcl, CocoTB, or similar verification automation tools. What We Need Develop and own scalable verification environmen

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Our Tensix Team is building the future of AI compute with a ground-up architecture centered on scalable RISC-V processors. As we push performance boundaries, we’re reimagining the frontend of our RISC-V cores to deliver major gains in programmability, efficiency, and developer experience. This is a rare opportunity to shape the CPU architecture at the heart of our AI platform and lead one of the most strategic technical efforts at Tenstorrent. This role is hybrid, based out of Toronto, ON, Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced Microarchitect: 10+ years of deep expertise in CPU performance modeling and microarchitecture design. AI Workload Expert: Deeply familiar with the computational and memory bottlenecks of modern AI workloads, particularly Large Language Models (LLMs). Hardware-Software Co-Designer: Driven to architect custom instruction set extensions and validate their performance gains against real-world workloads. Ways to stand-out: Familiarity with open-source RISC-V cores, AI-based agentic workflow experience What We Need Profile & Analyze: Dissect cutting-edge AI workloads to identi

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We're looking for an Engineering Program Manager — or a technical engineer ready to move into program management — to help drive execution on our RISC-V CPU team. You'll work across architecture, design, verification, physical design, and DFT to keep a high-performance CPU program moving from spec through tapeout and post-silicon debug. Partnering with a senior program lead and engineering managers, you'll own schedules, track milestones, surface risks early, and keep cross-functional teams aligned. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experience in CPU, SoC, or silicon development — as an engineer, technical lead, or program manager. Comfortable working with cross-functional engineering teams and translating technical detail into clear status, dependencies, and trade-offs. Organized and proactive; you chase down open items rather than waiting for them to resolve. A clear communicator who can hold your own in engineering discussions and write updates leadership can act on. What We Need Support the full CPU development cycle — spec, design, verification, DFT, ta