Partner Technology Solutions Engineer in United States

Partner Solutions Architect, Technology Partners Who we are About Stripe Stripe is a financial infrastructure platform for businesses. Millions of companies—from the world's largest enterprises to the most ambitious startups—use Stripe to accept payments, grow their revenue, and accelerate new business opportunities. Our mission is to increase the GDP of the internet, and we have a staggering amount of work ahead. That means you have an unprecedented opportunity to put the global economy within everyone's reach while doing the most important work of your career. About the team As a member of the Partner Solutions Architecture (PSA) team, you'll be responsible for providing technical guidance to Stripe's technology partners. Our goal is to drive growth through co-solutioning, education, and enablement with our partner organization. The right candidate will be a technical liaison to the Stripe Partner Development Manager. This will involve creating technical business plans for technology partners, including identifying, incubating, and bringing to market service and solution offerings built on or with Stripe. A Partner Solutions Architect is someone who is intellectually curious, open, and entrepreneurial. What you'll do As a member of the team, PSAs build consultative relationships with executives and technical decision-makers in the customer's organization to provide business and technical thought leadership, and become a trusted advisor in solving business-critical challenges. We architect business models with them so they can drive new monetization opportunities and growth. Responsibilities Work with key technology partners to build out their Stripe capabilities and solutions to grow their business and drive non-linear growth Develop and execute enablement plans Be at the forefront of technical discussions and solution deep-dives with technology partners on the value Stripe can provide to their clients Engage with CTOs, engineering, and other technical leads at ke

Who We Are About Stripe Stripe is a financial infrastructure platform for businesses. Millions of companies—from the world’s largest enterprises to the most ambitious startups—use Stripe to accept payments, grow their revenue, and accelerate new business opportunities. Our mission is to increase the GDP of the internet, and we have a staggering amount of work ahead. That means you have an unprecedented opportunity to put the global economy within everyone’s reach while doing the most important work of your career. About the team As a member of the Partner Solutions Architecture (PSA) team, you will be responsible for providing technical guidance to Stripe’s partners. Our goal is to drive growth through co-solutioning, education and enablement with our partner organization. The right candidate will be a critical technical liaison to the Stripe Partner Development Manager. This will involve creating comprehensive technical business plans for Partners, including identifying, incubating and bringing to market service/solution offerings built on or with Stripe. A Partner Solution Architect is someone who is intellectually curious, motivated to win, open and entrepreneurial. What you’ll do As a member of the team, PSAs build highly consultative trusted relationships with executives and technical decision makers in the customer’s organisation to provide business and technical thought leadership, and become a trusted advisor in solving mission-critical business challenges. We architect business models with them so they can drive new monetization opportunities and growth. Responsibilities: Work with key partners to build out their Stripe capabilities and solutions to grow their business and drive non-linear growth Develop and execute enablement plans Be at the forefront of technical discussions & solution deep-dives with partners on the value Stripe can provide to their clients Engage with CTOs, engineering & other technical leads at key partners to share technology

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which the GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As a Developer Technology Engineer you will be at the forefront of innovation, working with leading industry partners and exciting OSS projects to accelerate RTX & DGX SoC performance for agentic use. This role offers an outstanding opportunity to collaborate with world-class talent and make a significant contribution to the next era of enterprise and consumer AI. What you'll be doing: Own key engagements with our fast-paced developer ecosystem partners, optimizing their applications to deliver outstanding end-to-end performance on RTX and DGX SoCs. Take ownership of performance optimization for compute-intensive CPU, AI, and 3D graphics workloads, working with domain experts to identify bottlenecks and implement effective solutions. Work across system software, GPU driver, architecture, and NVIDIA Research teams to influence next-generation, high-performance SoC platforms by bringing real-world workflows and actionable insights from partner and customer needs. Provide technical guidance and mentorship to junior engineers while contributing to an inclusive and high-performing team environment. What we need to see: BS or MS degree in Computer Science, Engineering, Mathematics or related degree (or equivalent experience) 5+ years of respective work experience as software developer Proficiency in C/C++, Python, software

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an AI Reimagination Engineer in Micron's Generative AI Center of Excellence (GenAI COE), you have an outstanding chance to transform how businesses function. You will partner with different business areas to break down large, manual, multi-step processes and redesign them into effective, autonomous systems. This position combines process reimagination with AI systems engineering, making you a key part of the transformation journey. You will collaborate closely with the GenAI COE, IT architecture, security, and project teams. You will lead projects from the initial redesign to the final build, delivering solutions that business teams can adopt and scale. Responsibilities: Decompose end-to-end processes: Map current-state flows, quantify effort and risk, and lead eliminate/simplify/agentify analysis before automation. Architect the agentic solution: Build future-state flows and AI architecture, including task and agent decomposition, orchestration patterns, tool and data access, memory and context strategy, and human-in-the-loop controls. Translate inventions into buildable solutions by developing agent workflows, composing prompt and context strategies, MCP/connector and integration requirements, and evaluation criteria. Follow Micron's “Secure by Design”

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an AI Reimagination Engineer in Micron's Generative AI Center of Excellence (GenAI COE), you have an outstanding chance to transform how businesses function. You will partner with different business areas to break down large, manual, multi-step processes and redesign them into effective, autonomous systems. This position combines process reimagination with AI systems engineering, making you a key part of the transformation journey. You will collaborate closely with the GenAI COE, IT architecture, security, and project teams. You will lead projects from the initial redesign to the final build, delivering solutions that business teams can adopt and scale. Responsibilities: Decompose end-to-end processes: Map current-state flows, quantify effort and risk, and lead eliminate/simplify/agentify analysis before automation. Architect the agentic solution: Build future-state flows and AI architecture, including task and agent decomposition, orchestration patterns, tool and data access, memory and context strategy, and human-in-the-loop controls. Translate inventions into buildable solutions by developing agent workflows, composing prompt and context strategies, MCP/connector and integration requirements, and evaluation criteria. Follow Micron's “Secure by Design”

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an AI Reimagination Engineer in Micron's Generative AI Center of Excellence (GenAI COE), you have an outstanding chance to transform how businesses function. You will partner with different business areas to break down large, manual, multi-step processes and redesign them into effective, autonomous systems. This position combines process reimagination with AI systems engineering, making you a key part of the transformation journey. You will collaborate closely with the GenAI COE, IT architecture, security, and project teams. You will lead projects from the initial redesign to the final build, delivering solutions that business teams can adopt and scale. Responsibilities: Decompose end-to-end processes: Map current-state flows, quantify effort and risk, and lead eliminate/simplify/agentify analysis before automation. Architect the agentic solution: Build future-state flows and AI architecture, including task and agent decomposition, orchestration patterns, tool and data access, memory and context strategy, and human-in-the-loop controls. Translate inventions into buildable solutions by developing agent workflows, composing prompt and context strategies, MCP/connector and integration requirements, and evaluation criteria. Follow Micron's “Secure by Design”

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Advanced Packaging Technology Development (APTD) team at Micron is shaping the future of memory and storage technologies that fuel the AI era. We collaborate with global R&D groups, suppliers, and manufacturing teams to turn bold ideas into production-ready solutions. We innovate fast, learn continuously, and work as one team! This position is intended to be part of Micron's Technical Leadership Program (TLP). This is a career path for individuals seeking to advance as technical leaders and industry innovators. TLP members are expected to influence, lead, and mentor others. Position Overview: We are seeking an experienced organizational leader who will l ead and influence methodology improvements, including best practices in process development, data-driven decision-making, and application of AI/advanced analytics to drive innovation. In this role, you will drive strategic process development for Micron’s most advanced memory products, including HBM, 3DS DRAM, and emerging 3D architectures. You will guide end‑to‑end technology execution, partner across organizations, and influence both internal roadmaps and the external ecosystem. This is a high-impact role for someone who thrives at the intersection of innovation, complexity, and collaboration. Responsibilities: Own advanced packaging process technologies across wafer‑level and die‑level modules from pathfinding through manufacturing readiness Develop

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The TD Electrical Device Characterization team pushes the boundaries of Micron’s memory technology. We explore device behavior, uncover insights through data, and collaborate across engineering teams to enable next-generation products. We are a hands-on team that values curiosity, precision, technical rigor, and collaboration. In this role, you will drive electrical characterization for advanced memory technologies and partner with device, process, and product teams to turn measurements into actionable technical insights. Your work will help guide technology development and shape the performance and reliability of future NAND, DRAM, and emerging memory products. Responsibilities: Lead electrical characterization for advanced memory devices Develop measurement methods, algorithms, and scalable characterization standards Automate data pipelines and analysis using Python, JSL, C/C&#43;&#43;, and dashboard tools Architect test setups and manage wafer probe and ATE test flows Investigate device behavior, identify root causes, and communicate technical findings Minimum Qualifications: <span style="color:#6

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Engineer at Micron’s HBM New Product Validation team in Boise, ID you will be a senior technical guide responsible for validation strategy and readiness for future-generation High Bandwidth Memory (HBM) products. You will apply deep expertise in complex RAM and high-bandwidth memory architecture and building to establish architecture validation strategies. You will impact decisions that improve validation observability and debug efficiency . You will lead investigations of complex architecture, building , and silicon issues from pre-silicon simulation through post-silicon characterization. You will partner across Design Engineering, Design Validation, Product Engineering, Systems teams, and will develop and promote AI-enabled validation methodologies that improve efficiency, quality, and scalability. Responsibilities: Define architecture-aware validation strategies and coverage direction for future-generation HBM products. Drive validation readiness for next-generation products by preparing strategies, test environments, and execution plans before first silicon, reducing risk, accelerating issue resolution, and preventing late-stage surprises. Evaluate new DRAM/HBM architectural features and define validation requirements and testability needs before DBR. <span style="color:#

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The HBM Design Technology Package Co-Optimization (DTPCO) organization is seeking a Staff Engineer! Lead the design and development of test vehicles that enable technology learning and risk reduction for future HBM products! This role serves as a key technical contributor within DTPCO, partnering closely with Architecture, Design, Layout, Product Engineering, Reliability, and Advanced Packaging teams to translate emerging product requirements and technology challenges into actionable test vehicle solutions. You will apply expertise in semiconductor design, physical implementation, silicon characterization, and advanced packaging technologies to define test structures, develop validation strategies, and generate data that drives product decisions across future HBM generations. Unlike a traditional product role centered on ownership of product blocks, this position emphasizes enabling learning in development and engineering. It does so by developing representative test vehicles and characterization structures. Key Responsibilities Serve as a technical lead for HBM test vehicle design and structure development within DTPCO. Partner with HBM product, technology and reliability team. Define and implement test structures targeting key learning areas such as package interaction and reliability Drive test vehicle content definition, structure specifications, measurement requirements, and validation objectives. Analyze silicon characterization and qualification results to identify optimization opportunit

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Product Engineer in Node Development group, you will be part of a forward-thinking team of engineers that solves complex problems to develop industry leading DRAM! You will engage on new technology at design start and be part of a team responsible for delivering technology to enable the full product portfolio, initial device qualification and production ramp. This will be accomplished through innovation and by cross-functional engagement with partner groups; Design, Test, Technology Development, Marketing, Manufacturing and Quality Assurance departments to co-optimize product and process. While you may not exhibit all of the characteristics/skills listed below today, we are highly interested in a teammate who is motivated to grow in technical breadth and depth. Suppose you are open to learning while being a valued member of a team of world-class engineers. In that case, we are determined to help build upon your existing foundation, while focusing on your individual and collaborative skills in this exciting and outstanding opportunity. Responsibilities Include: Enable new process node startup, qualification, yield, and ramp Collaborate with internal engineering groups; Design, Technology Development, Design for Test, and Quality teams to understand yield issues and priorities. Provide direction to development teams using thorough knowledge for process integration Develop and key metrics for feedback on a new technology Support design verification and validation using CAD tools and simulation

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Our IP delivery timelines are set as much by flow maturity as by design work. This role develops, deploys, and owns the RTL-to-GDSII methodology the IP physical design team runs on, so a new block, node, or customer variant starts from a working flow instead of a cold start. This role is hybrid, based out of Toronto, ON; Austin, TX, or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A physical design or CAD methodology engineer who has built flows that production teams depend on daily. Automation-minded, happiest when you are removing manual steps and making PPA exploration repeatable. Building with AI as part of how you develop flows, and opinionated about where LLMs and ML-driven optimization genuinely help versus where they do not. An effective partner to design teams and EDA vendors, and a clear writer who documents flows well enough that others can run them without you. What We Need An Engineer with 5+ years developing and supporting physical design methodology or CAD flows in production use. Expertise with industry-standard tools (FusionCompiler/ICC2, Innovus/Genus, PrimeTime, RedHawk) and scripting languages (T

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer who will contribute to the physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout. You will partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs. Along the way, you will build end-to-end ASIC expertise while learning from experienced engineers across the chip development process. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An engineer excited to work on high-performance designs for industry-leading AI/ML architectures. A collaborative problem solver who enjoys working with experienced engineers across ASIC disciplines. Grounded in logic design fundamentals and gate- and transistor-level implementation. Curious about how early architectural and RTL decisions shape physical implementation and final chip quality. What We Need A BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a relat

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer with a strong background in static timing analysis (STA). In this role, you will help converge multi-million-gate designs on advanced process nodes and partner with cross-functional teams through final signoff and tapeout. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A physical design engineer with 8+ years of experience in STA, timing closure, and advanced-node design implementation. Experienced with timing flows, constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding, and final signoff. Skilled in writing and debugging SDC constraints, creating ECOs, developing closure strategies, and analyzing worst-case corners. A strong collaborator and communicator who can drive results across distributed, cross-functional engineering teams. What We Need Drive timing convergence across blocks, partitions, sections, and top-level designs; generate and validate timing models and publish results. Analyze timing violations, develop and propagate fixes, debug timing-flow issues, and

NVIDIA is looking for a hands-on Solutions Architect Manager to lead a team of GPU, networking & software solution architects and engineers. Do you want to build and lead a group that designs, debugs, and deploys new AI hardware and software technologies into production in customer data centers? As part of the NVIDIA SA organization, you will drive people and technical leadership for end-to-end solutions deployments at some of NVIDIA's most strategic technology customers, while directly contributing to designs and deep-dive debugging and shaping our product roadmap with customer feedback. What you will be doing: Recruit & manage a team of solutions architects, system/network and software engineers focused on large-scale GPU and AI networking deployments. Set priorities, allocate resources, mentor, and ensure high-quality customer delivery across multiple concurrent projects - while remaining directly involved in key technical reviews, design decisions, and critical debug efforts. Provide deep subject-matter expertise in advanced GPU and network systems and serve as the senior technical point of contact for strategic customers. Personally lead and guide complex compute/network configuration and performance debugging, working side-by-side with your team to deliver performant, reliable clusters. Guide your team as they lead network / compute / software architecture discussions, and support server, network, and cluster bring-up, including on-site data center work where needed. Systematically collect and synthesize customer-specific requirements across your portfolio. Partner with GPU/Network Systems Engineering, Product Management, and Sales to influence roadmap priorities and packaging of reference designs and solutions. Demonstrate SME in advanced GPU & network systems and be a trusted technical advisor to NVIDIA's strategic customers. Bring customer-sp