Powder Coater in United States

Work Flexibility: Onsite Schedule: Monday - Friday, 4:45am-1:15pm OT Required: 2 Saturdays per month What you will do: Paints and uses powder operations to properly prepare components that may include sub-assemblies and all other related components to contribute to completion of a variety of products Unloads parts, part racks, and hooks from the line while visually inspecting completed parts Applies painting and/or powder process in accordance with product specifications Sets paint/powder equipment for proper tolerances, color and feed rate Responsible for work preparation, clean up, and quality assurance of own work and work area Committed to quality by striving for reliability and quality in our products, continuously searching for ways to enhance performance and meeting all training and documentation criteria Strives for operational excellence by promoting a team-based, product-focused organization, contributing to continuous improvement, participating in preventative maintenance and safety programs, striving for cost reduction, and committing to on-time, complete, and error-free shipments Meet work schedule and overtime requirements, including weekends Must be able to lift/push/pull 50&#43; lbs throughout shift What you need Preferred High School or GED Manufacturing Experience $23.90 Hourly plus bonus eligible &#43; benefits Travel Percentage: None <p style=

Hyliion is committed to creating innovative solutions that enable clean, flexible and affordable electricity production. The Company’s primary focus is to develop distributed power generators that can operate on various fuel sources to future-proof against an ever-changing energy economy. Job Purpose The Senior Manager, Additive Fleet is responsible for the day-to-day performance of Hyliion's laser powder bed fusion (LPBF) printer fleet in Austin, which produces the complex, high-density metal heat exchanger hardware in the KARNO Core. This hardware can only be produced through metal additive manufacturing, so Hyliion's ability to build KARNO at scale depends directly on the health, uptime, and throughput of the fleet. The role leads the technicians and operators who run and maintain the machines, and owns preventive maintenance strategy, machine health monitoring, and decisions on hardware and software upgrades. The fleet runs the full range of Colibrium Additive LPBF platforms, including new machine technology being adopted in real time, and a primary focus is reducing machine-to-machine variation and building repeatable processes across machine models. This is a hands-on leadership role with regular time on the shop floor, and its scope will grow as Hyliion's print capacity scales. AI at Hyliion At Hyliion, AI is core to how we work. We equip every team member with leading AI tools and count on you to use them — to move faster, solve harder problems, and help us realize the full potential of KARNO technology for the world. Duties and Responsibilities Own fleet uptime and drive continuous improvement in machine-to-machine consistency across Hyliion's LPBF printer fleet. Build and maintain a preventive maintenance program across all machines to identify failure modes before they cause downtime. Lead, schedule, and develop the team of technicians and operators who run and maintain the fleet. Develop machine health monitoring us

About us EVERY™ is a leading VC-backed food tech ingredient company and market leader using precision fermentation to create animal proteins without the animal for the global food and beverage industry. EVERY™ is a team of passionate change-makers who are reimagining the factory farm model with a kinder, more sustainable alternative. Leveraging precision fermentation to produce hyper-functional and one-to-one replacement proteins from microorganisms, EVERY™ is on a mission to decouple the world’s proteins from the animals that make them. We are a passionate, determined (and fun!) team with a vital objective, and we're on the lookout for like-minded people to join our mission. For more information, visit www.every.com The Role: This unique entry-level Research Associate I position offers the rare chance to work across two core teams, Analytics and Protein Science. You’ll gain hands-on experience supporting protein development, purification, and analysis, while learning how these disciplines work together to drive innovation in precision fermentation. This is a great opportunity for someone early in their career who thrives in the lab, loves variety, and wants to learn fast in a collaborative, mission-driven environment. What you'll accomplish Generate data through basic biochemistry/molecular biology techniques (including but not limited to BCA, SDS-PAGE) Operate and maintain analytical equipment (e.g., HPLC-UV/RI and Combustion Analyzer, dynamic light scatterer, FPLC-UV, fluorescence/UV plate reader) Support protein characterization workflows through lab-scale protein powder generation involving bench-scale downstream processing unit operations (microfiltration, ultrafiltration, diafiltration) Prepare samples, reagents, and buffers to support cross-functional experiments Collaborate with scientists and engineers across teams to troubleshoot and iterate quickly as part of our Design, Build, Test, and Learn pipeline Present results

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology and amazing people. Today, we're harnessing the boundless possibilities of AI to build the next era of computing. An era in which our GPU acts as the brain of computers, robots, and self-driving cars that can understand the world. Accomplishing unprecedented goals calls for imagination, inventiveness, and exceptional talent from around the world. As a NVIDIAN, you'll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Join our team and discover how you can build a lasting impact on the world. NVIDIA designs the silicon behind AI, accelerated computing, and graphics. Power and thermal architecture decisions sit behind every watt of performance and every degree of thermal headroom! We are the Silicon Co-Design Group (SCG). We are hiring a Principal Architect to scout the research and industry landscape, identify emerging system-level co-design ideas in power and thermal, and drive them across teams into product differentiation across NVIDIA's roadmap. This role shapes system, platform, and datacenter feature/behavior, and partners with teams across Nvidia. SCG scope spans across architecture, design, software, operations, platforms, and productization. What you'll be doing: Architect next-generation system, platform, and datacenter-level power and thermal co-design solutions. Scan internal research, academia, standards bodies, and silicon, memory, packaging, and platform partners for what is emerging. Build the product differentiation case for each candidate idea, performance, power, reliability, schedule, cost, and brainstorm what is worth pursuing. Lead end-to-end co-design from concept to product. Drive alignment across architecture, VLSI, softw

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Our Tensix Team is building the next generation of high-performance AI compute systems. We’re looking for a Power Architect to drive architectural strategy, modeling, and design decisions that shape how power is understood and optimized across our products. This is a hands-on role with massive influence over how we build power-aware systems from the ground up. This role is hybrid, based out of Santa Clara, CA, Boston, MA, Austin, TX or Toronto. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are 15+ years experience with power estimation tools like PowerArtist, PtPX, RTL Architect, and PrimePower. Skilled in modeling and optimizing power at the architectural level, with deep knowledge of power-gating, voltage domains, and leakage control. Track record of influencing architectural and micro-architectural changes that meaningfully reduced design power. Proficient in Verilog HDL, Design Compiler, C/C++ and Python. Background in power-optimization of compute datapath and/or interconnects. What We Need Predict power consumption early in architecture and track it through RTL evolution. Propose architectural changes for power optimization across server and non-

Power and Performance Validation Engineer About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations. This role requires strong technical expertise and collaboration across multiple engineering disciplines to deliver robust validation methodologies, scalable automation frameworks and actionable performance insights. The Team The Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems. The team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debug compl

About the Team OpenAI, in close collaboration with our capital partners, is building the world’s most advanced AI infrastructure ecosystem. The Power & Land team owns the energy strategy required to secure reliable, scalable, and economically resilient power for OpenAI’s global data center portfolio. About the Role The Power Trading Lead will own commodity hedging strategy and execution across OpenAI’s data center power portfolio. This role will translate large, dynamic electricity and fuel exposures into practical hedging, procurement, and risk-management strategies that protect infrastructure economics while preserving flexibility for growth. This is an individual contributor lead role and does not have direct reports initially. The role will work across power markets, utility tariffs, retail and wholesale supply structures, natural gas and power hedges, renewable and clean firm products, and portfolio risk analytics to support long-term compute growth. Key Responsibilities Develop and maintain OpenAI’s commodity hedging strategy across electricity, natural gas, and related energy exposures for data center operations and growth. Quantify portfolio exposure by market, site, load shape, tenor, tariff, and supply structure, and translate that exposure into clear hedging recommendations. Evaluate and execute hedging structures including fixed-price supply, forwards, swaps, options, retail supply products, congestion and basis risk mitigation, and related instruments where appropriate. Partner with utilities, suppliers, traders, banks, consultants, and market counterparties to source competitive products and improve risk-adjusted energy economics. Build decision frameworks for when to hedge, how much to hedge, and which risks to retain across different stages of site development, construction, and operations. Coordinate with finance, treasury, legal, procurement, energy regulatory, sustainability, and site-readiness teams to ensure hedging strategy aligns with broa

About the Team OpenAI, in close collaboration with our capital partners, is building the world’s most advanced AI infrastructure ecosystem. The Site Readiness & Development team owns the upstream diligence and development work required to convert powered-land opportunities into executable infrastructure options. About the Role The Power Land Developer; Development & Power Projects will support the advancement of powered-land opportunities across the portfolio, reporting to the Development & Power Project Lead. This is an individual contributor lead role and does not have direct reports initially. This role will own day-to-day development execution across approximately 1–3 active sites depending on complexity, including utility applications, interconnection requests, study follow-through, queue milestones, consultant workstreams, schedule and risk management, and readiness handoff for opportunities advancing to deeper diligence, commercial commitment, or execution. The role translates study and utility findings into clear schedule, budget, and risk implications for portfolio decisions. Responsibilities Manage day-to-day advancement of powered-land opportunities from intake through readiness. Own utility application and interconnection follow-through across active powered-land opportunities, including utility inputs, study responses, and queue milestones. Scope and manage external studies and consultant workstreams needed to validate readiness. Track development schedules, dependencies, risk registers, site-readiness milestones, and key budget implications. Translate technical findings into clear schedule, budget, and risk implications and escalate material blockers or trade-offs to the Development & Power Project Lead. Partner with land, environmental, economic development, and community affairs leads to align project advancement. Support expansion planning, infrastructure sequencing, and long-term power-risk mitigation. Define readiness criteria and

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for a Rack Power Engineer with deep expertise in high-power conversion and distribution to design, qualify, and support power systems for AI supercomputers. You will own rack power solutions—including power shelves, AC/DC rectifiers, power supply units (PSUs), power management controllers (PMCs), and high-current distribution—from requirements and supplier development through deployment. You will also monitor fleet rack power health, lead debugging and root-cause investigations, and drive improvements into hardware, firmware, and qualification coverage. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own rack power architecture and requirements for high-power AI supercomputing systems, including power budgets, AC input interfaces, DC distribution, redundancy, efficiency, serviceability, and integration with data center infrastructure. Drive the design and supplier development of power shelves, rectifiers, PSUs, PMCs, busbars, connectors, and protection circuits. Review electrical designs and control behavior, and evaluate performance, cost, reliability, and availability trade-offs. Define and execute component, shelf, and rack qualification plans covering load transients, current sharing, hot-swap, startup and shutdown, redundancy failover, fault protection and recovery, thermal limits, and AC disturbances and ride-through

The SCG Architecture team is hiring a Senior Power Integrity Co-Design Engineer to architect and deliver di/dt mitigation across silicon, package, board, and platform. This role bridges architecture, silicon, and platform — translating product noise targets into shipped specifications, and feeding silicon findings back into the next generation's build. Success in this role requires strong systems thinking and a willingness to accept ambiguity. It also requires the ability to apply AI as a force multiplier while maintaining rigorous engineering judgment. What you'll be doing: Architect voltage-noise mitigation across the full stack — silicon, package, board, platform — and own the codesign trade-offs between them. Co-design noise features with Speed, Power, Reliability, Circuit Design , Power-Arch, ASIC, and platform teams. You're the connective tissue across the codesign web. Work with other team members to define product-level voltage noise targets, drive them to closure, and sign them off at shipment. Build and take ownership of the Sim-to-Si correlation methodology for noise. You know when a model is lying and when silicon is. Model and prototype next-gen noise features — transient sense, droop response, mitigation IP, and codify them so every future program inherits them. Lead show-stopper noise bugs during bringup. The critical issues stop with you. Drive architecture-level codesign tradeoffs across V/F Power Noise Reliability Thermal (Noise-Variation) and (Noise-to-Closure) boundary work, where the highest-leverage innovation lives. What we need to see: BS / MS / PhD in EE, CE, or related (or equivalent experience). 5&#43; years in silicon power integrity, voltage noise, or PDN. Deep expertise in at least one of

NVIDIA's Silicon Co-design Group (SCG) sits at a rare intersection: we own the full product development lifecycle, from early architecture definition through silicon bringup to product release. Our ArchDev team is the hub for silicon and system-level feature development, driving tradeoff analysis, system integration, and POR alignment across the entire organization. If you want to see your work go from whiteboard to world-class silicon, this is where that happens. What You'll Be Doing: Architect and integrate system-level performance and power management features, controllers, and policies to optimize product efficiency across datacenter and client products . Build feature roadmaps to address low-power, low-noise, and performance-per-watt product needs through prototyping, use-case analysis, and cost/benefit trade-offs. Partner with architecture, ASIC, board/platform, software/firmware, and marketing teams to drive design decisions and debug complex issues. Track industry trends and market needs and translate them into forward-looking roadmaps that keep NVIDIA's products ahead of the curve. Lead debug efforts, develop workarounds, and support bringup , validation, manufacturing, and customer escalations. What We Need to See: <

Job Details: Job Description: As a Senior Power and Performance (PnP) Engineer, you will be responsible for PnP product execution focused on measurements, analysis, and projections/estimates of Intel's unlaunched notebook and desktop products. Based on your technical knowledge of both Intel and the competition, you will help influence OEM customers, internal marketing teams, internal engineering teams, debug Intel silicon/platform on PnP issues, and be an integral part for Intel product launches. Core responsibilities to include following: Measure, analyze, and debug workloads to call out any power and/or performance gaps and close with internal engineering teams/architects Measure and analyze SoC/CPU and platform power on a rail by rail basis and debug any issues/gaps Align with other internal engineering teams and architects to ensure there is consensus on power and performance projections/estimates/measurements for both internal and external communication Guide, educate, and influence internal engineering teams, field account teams, and marketing teams on power and performance positioning of Intel products Create power and performance estimates on upcoming Intel products based on workloads to aid marketing decisions and help set internal KPI targets Own the publication of the Power Performance Guide (PPG) collateral to help guide OEM customers Bring up full test platform to enable both power and performance measurements including setup, calibration, and measurements. Qualifications: You mus

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a highly skilled and experienced Engineer to lead post-silicon power characterization and correlation activities for cutting-edge semiconductor products. In this role, you will be responsible for developing and executing detailed power measurement strategies on silicon, correlating results with pre-silicon models, and driving improvements across power architecture, design, and modeling methodologies. You will serve as a key technical leader, interfacing across design, architecture, validation, and systems teams to ensure silicon meets power and performance specifications under all operating conditions. This role is hybrid, based out of Toronto, ON or Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are A Principal-level engineer with 8+ years in silicon power analysis and characterization, and a Master’s or PhD in EE, CE, or related field. Deep understanding of digital and mixed-signal power domains, including DVFS, leakage vs. dynamic power, and power gating. Highly proficient in lab-based power measurement using oscilloscopes, current probes, power analyzers, and SMUs, plus Python/Perl/MATLAB

Staff -Power and Performance Validation Engineer About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations. This role requires strong technical expertise and collaboration across multiple engineering disciplines to deliver robust validation methodologies, scalable automation frameworks and actionable performance insights. The Team The Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems. The team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debu

About the Team OpenAI's mission is to ensure that artificial general intelligence benefits all of humanity. The Consumer Devices team is building a new generation of AI-powered products that seamlessly integrate hardware and software to create intuitive, transformative experiences. We bring together experts across embedded systems, machine learning, hardware, design, and product engineering to develop products at the intersection of AI and consumer technology. About the Role OpenAI is seeking a System Power Engineer to characterize, measure, and optimize power consumption across our embedded hardware products. In this role, you will work closely with Electrical Engineering and system software teams to build power test automation, measure subsystem-level power usage, and drive improvements that directly impact battery life, thermal behavior, charging performance, and system reliability. You will help establish the methodologies and metrics used to understand and improve power efficiency across real-world product experiences, from controlled lab environments to representative day-in-the-life usage scenarios. This role requires hands-on experience with embedded hardware platforms, power instrumentation, and the analysis of power profiles and system behavior. This role is based in San Francisco, CA. We use a hybrid work model of four days per week in the office and one day working remotely. Relocation assistance is available for new hires. In this role, you will: Define and develop power testing automation to evaluate system behavior across a range of workloads and operating conditions. Measure subsystem-level power consumption using power breakout probes and other lab instrumentation. Develop and execute power characterization tests spanning basic workloads, complex mixed-use scenarios, and representative day-of-use experiences. Partner closely with Electrical Engineers to identify opportunities to improve system power efficiency. Collaborate with software engineering