Power Integrity Engineer in United States

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Our Tensix Team is building the next generation of high-performance AI compute systems. We’re looking for a Power Architect to drive architectural strategy, modeling, and design decisions that shape how power is understood and optimized across our products. This is a hands-on role with massive influence over how we build power-aware systems from the ground up. This role is hybrid, based out of Santa Clara, CA, Boston, MA, Austin, TX or Toronto. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are 15+ years experience with power estimation tools like PowerArtist, PtPX, RTL Architect, and PrimePower. Skilled in modeling and optimizing power at the architectural level, with deep knowledge of power-gating, voltage domains, and leakage control. Track record of influencing architectural and micro-architectural changes that meaningfully reduced design power. Proficient in Verilog HDL, Design Compiler, C/C++ and Python. Background in power-optimization of compute datapath and/or interconnects. What We Need Predict power consumption early in architecture and track it through RTL evolution. Propose architectural changes for power optimization across server and non-

Power and Performance Validation Engineer About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations. This role requires strong technical expertise and collaboration across multiple engineering disciplines to deliver robust validation methodologies, scalable automation frameworks and actionable performance insights. The Team The Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems. The team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debug compl

About the Team OpenAI, in close collaboration with our capital partners, is building the world’s most advanced AI infrastructure ecosystem. The Power & Land team owns the energy strategy required to secure reliable, scalable, and economically resilient power for OpenAI’s global data center portfolio. About the Role The Power Trading Lead will own commodity hedging strategy and execution across OpenAI’s data center power portfolio. This role will translate large, dynamic electricity and fuel exposures into practical hedging, procurement, and risk-management strategies that protect infrastructure economics while preserving flexibility for growth. This is an individual contributor lead role and does not have direct reports initially. The role will work across power markets, utility tariffs, retail and wholesale supply structures, natural gas and power hedges, renewable and clean firm products, and portfolio risk analytics to support long-term compute growth. Key Responsibilities Develop and maintain OpenAI’s commodity hedging strategy across electricity, natural gas, and related energy exposures for data center operations and growth. Quantify portfolio exposure by market, site, load shape, tenor, tariff, and supply structure, and translate that exposure into clear hedging recommendations. Evaluate and execute hedging structures including fixed-price supply, forwards, swaps, options, retail supply products, congestion and basis risk mitigation, and related instruments where appropriate. Partner with utilities, suppliers, traders, banks, consultants, and market counterparties to source competitive products and improve risk-adjusted energy economics. Build decision frameworks for when to hedge, how much to hedge, and which risks to retain across different stages of site development, construction, and operations. Coordinate with finance, treasury, legal, procurement, energy regulatory, sustainability, and site-readiness teams to ensure hedging strategy aligns with broa

About the Team OpenAI, in close collaboration with our capital partners, is building the world’s most advanced AI infrastructure ecosystem. The Site Readiness & Development team owns the upstream diligence and development work required to convert powered-land opportunities into executable infrastructure options. About the Role The Power Land Developer; Development & Power Projects will support the advancement of powered-land opportunities across the portfolio, reporting to the Development & Power Project Lead. This is an individual contributor lead role and does not have direct reports initially. This role will own day-to-day development execution across approximately 1–3 active sites depending on complexity, including utility applications, interconnection requests, study follow-through, queue milestones, consultant workstreams, schedule and risk management, and readiness handoff for opportunities advancing to deeper diligence, commercial commitment, or execution. The role translates study and utility findings into clear schedule, budget, and risk implications for portfolio decisions. Responsibilities Manage day-to-day advancement of powered-land opportunities from intake through readiness. Own utility application and interconnection follow-through across active powered-land opportunities, including utility inputs, study responses, and queue milestones. Scope and manage external studies and consultant workstreams needed to validate readiness. Track development schedules, dependencies, risk registers, site-readiness milestones, and key budget implications. Translate technical findings into clear schedule, budget, and risk implications and escalate material blockers or trade-offs to the Development & Power Project Lead. Partner with land, environmental, economic development, and community affairs leads to align project advancement. Support expansion planning, infrastructure sequencing, and long-term power-risk mitigation. Define readiness criteria and

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for a Rack Power Engineer with deep expertise in high-power conversion and distribution to design, qualify, and support power systems for AI supercomputers. You will own rack power solutions—including power shelves, AC/DC rectifiers, power supply units (PSUs), power management controllers (PMCs), and high-current distribution—from requirements and supplier development through deployment. You will also monitor fleet rack power health, lead debugging and root-cause investigations, and drive improvements into hardware, firmware, and qualification coverage. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own rack power architecture and requirements for high-power AI supercomputing systems, including power budgets, AC input interfaces, DC distribution, redundancy, efficiency, serviceability, and integration with data center infrastructure. Drive the design and supplier development of power shelves, rectifiers, PSUs, PMCs, busbars, connectors, and protection circuits. Review electrical designs and control behavior, and evaluate performance, cost, reliability, and availability trade-offs. Define and execute component, shelf, and rack qualification plans covering load transients, current sharing, hot-swap, startup and shutdown, redundancy failover, fault protection and recovery, thermal limits, and AC disturbances and ride-through

Job Details: Job Description: As a Senior Power and Performance (PnP) Engineer, you will be responsible for PnP product execution focused on measurements, analysis, and projections/estimates of Intel's unlaunched notebook and desktop products. Based on your technical knowledge of both Intel and the competition, you will help influence OEM customers, internal marketing teams, internal engineering teams, debug Intel silicon/platform on PnP issues, and be an integral part for Intel product launches. Core responsibilities to include following: Measure, analyze, and debug workloads to call out any power and/or performance gaps and close with internal engineering teams/architects Measure and analyze SoC/CPU and platform power on a rail by rail basis and debug any issues/gaps Align with other internal engineering teams and architects to ensure there is consensus on power and performance projections/estimates/measurements for both internal and external communication Guide, educate, and influence internal engineering teams, field account teams, and marketing teams on power and performance positioning of Intel products Create power and performance estimates on upcoming Intel products based on workloads to aid marketing decisions and help set internal KPI targets Own the publication of the Power Performance Guide (PPG) collateral to help guide OEM customers Bring up full test platform to enable both power and performance measurements including setup, calibration, and measurements. Qualifications: You mus

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a highly skilled and experienced Engineer to lead post-silicon power characterization and correlation activities for cutting-edge semiconductor products. In this role, you will be responsible for developing and executing detailed power measurement strategies on silicon, correlating results with pre-silicon models, and driving improvements across power architecture, design, and modeling methodologies. You will serve as a key technical leader, interfacing across design, architecture, validation, and systems teams to ensure silicon meets power and performance specifications under all operating conditions. This role is hybrid, based out of Toronto, ON or Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are A Principal-level engineer with 8+ years in silicon power analysis and characterization, and a Master’s or PhD in EE, CE, or related field. Deep understanding of digital and mixed-signal power domains, including DVFS, leakage vs. dynamic power, and power gating. Highly proficient in lab-based power measurement using oscilloscopes, current probes, power analyzers, and SMUs, plus Python/Perl/MATLAB

Staff -Power and Performance Validation Engineer About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations. This role requires strong technical expertise and collaboration across multiple engineering disciplines to deliver robust validation methodologies, scalable automation frameworks and actionable performance insights. The Team The Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems. The team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debu

Job Details: Job Description: Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below. Life at Intel The Role and Impact As a SoC Power Thermal Performance Validation and Optimization Engineer, you will play an essential role in ensuring Intel's products achieve optimal power, thermal, and performance benchmarks at the system-on-chip (SoC) level. In this position, you will develop and execute validation methodologies, optimize hardware/software solutions, and perform SoC-level debugging to address power, thermal, and performance challenges. Your contribution will directly impact Intel's ability to deliver competitive, high-performing products to market. Business Group This role is part of Intel's Data Center Group (DCG), which focuses on designing innovative solutions to power the next generation of computing platforms for data centers. As a member of the PTP PreSi Correlation Solution team, you will contribute to shaping the development and validation processes for cutting-edge technologies, ensuring Intel meets and exceeds industry standards for performance and efficiency. Key Responsibilities: Develop and execute SoC-level power, thermal, and performance validation and

Partner Business Manager (PBM) Power Elite Description - The Partner Business Manager (PBM) is responsible for managing relationships with Tier-2 resellers, staying updated on market insights, and driving business growth through data-driven insights. This role focuses on ensuring strong strategic relationships, achieving business objectives, and promoting HP offerings. PBM will drive business growth through the Amplify program and GBU initiatives, strong partner engagement with HP, strategic relationship between reseller and HP towards becoming OEM of choice, increase HP Share of Wallet with partners. Key Responsibilities Coordinate peer-to-peer engagement between partner teams and HP end-user sales organizations to expand the customer funnel, accelerate pipeline growth, and drive revenue growth through partner-led selling motions. Represent HP at partner-led events and sales engagements, educating, inspiring, and enabling partner sellers to effectively articulate and champion HP’s Future of Work strategy. Manage relationships with assigned Commercial Tier-2 resellers. Stay updated with market and industry insights, expertly align HP business objectives with partner capabilities, identify market trends, and turn them into actionable business opportunities. Consult partners on growth and transformation strategies, collaborate with partner and HP sales teams, generate data-driven insights, and create joint business plans to promote sales growth. Enable and develop partners' understanding of actions they need to grow their business in strategic alignment with HP. Lead the orchestration of HP’s ecosystem as the "point-guard"—driving strategic relationships, engaging in partners' co-selling efforts, resolving challenges, shifting pa

NVIDIA has been redefining computer graphics, desktop gaming, and enhanced computing capabilities for more than 25 years. Today, we are tapping into the unlimited potential of AI to define the next era of computing. As a NVIDIAN, you will work on problems that sit at the boundary of architecture, silicon, firmware, software, and production, where strong judgment matters as much as technical depth. We're the Silicon Design for Productization (DFP) Team, within the broader Silicon Co-Design Group, and we turn power and thermal design into executable productization methodology. Power and thermal are among the most complicated problems we work on at NVIDIA because they sit at the intersection of architecture, workload behavior, silicon variation, firmware policy, platform constraints, and product goals. Small decisions here have an outsized impact on performance, efficiency, reliability, bring-up speed, and ultimately what the product can deliver in the field. We define how features move from concepts to bring-up, characterization, validation, and release. In this role, you will help us build that bridge. We're looking for an engineer who reasons from first principles, flourishes with ownership in a fast-paced environment, and uses AI with sound judgment. What you’ll be doing: Lead the effort across multi-functional teams to keep the program’s power and thermal productization strategy clear, executable, and on track. Create methodology and silicon test plan based controller designs and architecture, including characterization process, debug tools, fuse/firmware settings and lab requirements. Drive resolution for challenging silicon issues through structured hypotheses, measurement plans, and root-cause closure. Steward the Power and Thermal playbook when the existing productization methodology

Work Flexibility: Field-based Field Service Technician – Power Tools As a Field Service Technician supporting Power Tools, you will serve as a key technical resource for healthcare customers across your assigned territory. This field-based role focuses on equipment service, troubleshooting, maintenance, and documentation, with most of your time spent traveling in a company-provided vehicle between customer sites, resolving technical issues, and ensuring equipment performs as intended. Success in this role depends on delivering a positive customer experience through effective service support, clear communication, accurate documentation, and strong collaboration with healthcare customers, clinical staff, sales partners, and internal stakeholders. This role requires the ability to manage multiple service priorities, work independently in customer environments that can be fast-paced or stressful, and collaborate with internal partners when additional support or coordination is needed. What You Will Do Develop and maintain strong relationships with customers and internal partners, including sales and commercial teams, to deliver exceptional customer experiences, ensure optimal equipment performance, and support business goals within the assigned territory. Travel to hospitals and healthcare facilities to complete assigned service requests, installations, and preventive maintenance activities. Troubleshoot, diagnose, and repair equipment issues to restore functionality and minimize downtime. Install, maintain, and inspect medical equipment in accordance with service guidelines and quality standards. Support software, connectivity, and system configuration activities as required to maintain equipment performance. Coordinate service schedules, prioritize customer requests, communicate service findings and recom

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. Design-for-X Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions in AI for Chip Design and AI for Predictions in various use cases in manufacturing testing on some of the industry's most complex semiconductor chips. What you'll be doing: As a senior member in our team, you will work on innovating in the DFT Power, Thermal & Voltage Noise Methodology areas. This will include working on groundbreaking low power & thermal solutions for our manufacturing tests to be enabled at conditions that push the boundaries for our datacenter GPUs. You will work with multi-functional teams including Product Development & Power Architecture, implementing brand-new methodologies on hard-to-solve problems for improving our outgoing quality of chips. You will work on post-silicon data analysis for power to architect the next-gen solutions. In addition, you will help develop and deploy DFT methodologies for our next generation products using Applied ML & Gen AI solutions. You will also help mentor junior engineers on test designs and trade-offs including cost and quality. What we need to see: BSEE (or equ

NVIDIA builds the silicon behind AI, accelerated computing, and graphics. Every watt of performance and every degree of thermal headroom traces back to decisions made in power, performance, and thermal architecture. We are the Silicon Co-Design Group (SCG). We identify, own, and drive system-level co-design ideas. We start with initial concepts and advance to product differentiation across NVIDIA's roadmap. We are hiring a Principal System Power Management and Performance Architect who operates at the ambiguous boundary where workload behavior, silicon capabilities, firmware policies, and platform constraints collide, and who turns that ambiguity into architecture that survives across multiple silicon generations. SCG scope spans architecture, design, software, operations, platforms, and productization. This role shapes system, platform, and data center features and behavior, and partners with teams across NVIDIA. What You'll Be Doing: The work here is rarely well-defined when it arrives. You will be given problems that appear to be performance gaps or power anomalies and encouraged to build a framework for solving them, not just tackle a single instance. Define the multi-generation roadmap for system-level power and performance features, grounded in prototyping, use-case analysis, and cost/benefit trade-offs across segments. You will decide what problems are worth solving and why. Own the architecture and integration strategy for HSIO power management, DVFS, P-states, and low-power features. Your decisions improve product performance, power, and reliability across product lines — not just the current program. Lead system-level boot and IST architecture defining how power and clock domains initialize, sequence, and recover across complex multi-IP systems where the interaction space is large and the failure modes matter. Drive power management strategy at data

Data Center Power Test Architect — US, CA, Santa Clara. Apply via Workday.