Product Service Coordinator in United States

Who We Are Notion is the collaborative AI workspace where teams and agents think together . We're building one place where your knowledge, projects, meetings, and AI tools live side by side, so work is faster, clearer, and less fragmented. Millions of individuals, small teams, and large companies run their work on Notion. Notinos (our employees) are customer zero in bringing this future of work to life. We care about craft, building things that last, and the belief that great work is still fundamentally human. Our goal isn’t to ship the next feature. Each and every team of Notinos is working to set the standard for how humans work together in the AI era. From building a business’s system of record to making and managing AI agents to automating away the busy work, we care deeply about giving our customers more time for their life’s work. About the Role: The People Team at Notion exists to help build a generational company that enables people to do their best and most meaningful work. This role operates at all altitudes - one minute, you’ll be building a people strategy with a member of our leadership team, and the next, you’ll be coaching an employee. With Notion's scale this year, you'll play a major role in how we shape, mold, and build the future of Notion for years to come. This role is based in San Francisco, CA. We work from our offices on Mondays, Tuesdays and Thursdays (our Anchor Days) because we do our best thinking and building together in person. We’re looking for someone who’s excited to work alongside the team during those days. What You'll Achieve: Build deep partnerships with Notion’s leadership team (especially across Engineering, Product, and Design), and serve as a conduit between stakeholders up to C-suite and the People Team. Advise on, create, and execute people strategies that drive the business forward. Consult with the leadership team on Talent Planning, Org Design, Retention Strategies, and Change Management. Apply systems thinking to evolve

Job Details: Job Description: Responsible for managing the relationship between Intel Data Center and AI (DCAI) and Dell ISG with focus on driving sales strategy of existing Xeon and AI product offerings while expanding Intel design portfolio within Dell's future roadmap to ensure the acceleration of Xeon and AI adoption. Through the design-in process, demonstrate the skills to showcase a quantifiable preference to Intel technology and integrate key learnings into Intel and Dell marketing organizations. The role is critical to establish great relationships and trust with key individuals at Dell and Intel business units and help both companies understand each other's challenges, opportunities to work towards a solution(s) that allows both companies to succeed. The candidate will have enough technical depth to understand the Intel product roadmap, the customer roadmap needs and what the competition is offering and intelligently recommend how to sell the Intel value proposition. Key Responsibilities include: Serve as sales and technical lead for multiple Dell PowerEdge and AI server programs based on Intel Xeon processors and AI accelerators, and collaborate with marketing team to drive complete end-to-end execution. Partner closely with Intel and Dell engineering, product, marketing, and program teams worldwide to align on features, schedules, quality, and issue resolution, ensuring successful product execution. Drive strategic design-win engagements for future Intel Xeon and AI accelerator products, influencing both Intel and Dell roadmaps through deep customer insight, competitive analysis, and early requirements gathering. Act as the primary interface between Intel and Dell, rapidly resolving business and technical issues, managing escalations, and ensuring the highest levels of cus

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s DRAM Product Architecture Group partners across fabs, test, module, and system teams worldwide to deliver high-performance memory products. We work across geographies and functions to solve complex technical challenges, drive product innovation, and enable industry-leading DRAM solutions. Our team values collaboration, continuous learning, and making a measurable impact through engineering excellence. As a New College Graduate DRAM Yield & Quality Engineer, you will play a key role in monitoring and improving the health of Micron’s server DRAM products. Working with experienced engineers and cross-functional teams around the globe, you will analyze product and manufacturing data, investigate technical issues, and contribute to strategies that improve yield, quality, and performance throughout the product lifecycle. This is a highly visible role with direct impact on customer success and product reliability. Responsibilities Analyze silicon parametric, test, and manufacturing data to identify trends, resolve product issues, and support root cause investigations. Contribute to yield and quality improvement initiatives across new product introduction (NPI), qualification, ramp, and high-volume manufacturing. Collaborate with fab, test, module, quality, and operations teams to drive execution of product health objectives. Develop and maintain automation solutions to improve engineering efficiency, data analysis, and reporting. Apply AI, Agentic AI, and Generative AI tools to en

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Staff Design Engineer is responsible for designing, simulating, and optimizing DRAM circuits while supporting the development of digital and analog circuitry used in advanced memory products. This role collaborates globally across design, verification, product engineering, test, probe, process integration, assembly, and marketing to ensure manufacturable, high‑quality, cost‑optimized solutions. The position drives innovation in future memory generations and contributes to silicon‑to‑system development in a dynamic engineering environment. Responsibilities Design digital, analog, and memory core circuits using CMOS logic and transistors, implementing device specifications from concept to solution. Utilize AI-Enabled tools to assist with schematic editing, data collection and layout floorplan. Create optimized floorplans for circuit placement, routing, power delivery, sense margins, array timing, and die size, including layout leadership. Conduct circuit simulations using FINESIM, HSPICE, and VERILOG; analyze power, performance, reliability, and parasitic impacts. Validate builds through reticle experiments, tape‑out revisions, and simulation‑to‑silicon correlation, identifying required schematic edits. Prepare and maintain design documentation while contributing to best‑known practices and departmental training. Collaborate with global build, verification, product engineering, test, probe, process integration, assembly, and marketing teams to ensure manufacturability and quality. <l

NPI Mechanical Quality Engineer Description - As part of the Personal Systems Quality organization, the NPI Mechanical Quality Engineer drives product quality and reliability throughout the NPI product development lifecycle. This role partners with cross-functional teams to evaluate designs, identify and mitigate reliability risks, drive failure analysis and root cause investigations, and implement corrective actions that improve product quality and customer experience. This role provides technical leadership in reliability test development, mechanical design assessment, and Design for Quality and Reliability (DFX) initiatives to ensure high-quality products from concept through production. Strong mechanical engineering expertise, problem-solving skills, and team collaboration are essential for success in this role. *Onsite in Spring office is required 4-days a week Responsibilities: • Provides technical analysis of compute products during NPI Phase through RFQ design proposal reviews, CAD reviews, and DFX product tear downs. • Provides advanced failure analysis, root cause identification, and corrective/preventive actions for reliability concerns and/or issues during development, manufacturing, and field operations. • Proactively addresses customer requests or issues related to mechanical reliability, ensuring timely resolution while liaising with the relevant stakeholders. • Provides consultation to product development architecture teams regarding material component selection, design risk assessment, and associated reliability test plans. • Provides NUD (new, unique, difficult) risk mitigation and test plan development and develops issue prevention. • Actively mentors less-experienced engineers in the field of mechanical reliability and contributes to their growth in the organization. Education & Expe

NVIDIA’s Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first-principles thinking and engineering judgment at the highest level translate directly into product outcomes at scale. We are looking for a Principal Performance and Manufacturing Architect who has built the models, defined the specs, and seen them validated through silicon. You have owned the connection between design intent and manufacturing reality, not as a reviewer or a contributor, but as the person who set the methodology and proved it worked. You turn ambiguous physical phenomena into quantified, defensible margin terms. You do not wait for data to confirm your hypothesis; you design the experiment that gets it. You improve how the organization ships products after every program. The exceptional hire also uses AI deliberately — with proven workflow impact and the judgment to know where it compresses real work and where it introduces risk. What you'll be doing: Own the physics, from mechanism to margin. Build first-principles models connecting AVF, defect mechanisms, and DVFS transients to field FIT, system-level yield, and DPPM vs. coverage — calibrated per node and population shift — so every margin term in the V/F curve and P-state table is named, sourced, and defensible. Set the screen that resolves escapes. Specify ATE and SLT voltage, frequency, and timing conditions that capture worst-case transient VF windows — making it unambiguous whether a marginal defect or timing violation is detected or escapes at every manufacturing stage. Make the POR the authoritative source. Author the methodology document for each program and drive alignment across build, product definition, reliability, and test engineering — so every team is making decisions from the same model. Prove the model before produc

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. NVIDIA’s Silicon Co-Design Group is hiring a Chip Lead to serve as the technical lead for one of our most consequential silicon programs! This is not project management, and it is not a senior IC role. You are the person the program partners with on its hardest technical questions — when the right answer is not obvious, and when leadership needs a single technical perspective to align on direction. You are accountable for the technical integrity of the chip end-to-end. You guide co-design feature integration, help resolve the toughest multi-functional bugs, and serve as the project-specific custodian of the qualification playbook. The program runs cleaner because you are on it! What you’ll be doing: You will partner across design, validation, software, and manufacturing to keep the program’s technical narrative clear and on track. Day to day, you will: Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs. Co-lead program-level feature integration from chip to system, surfacing inter-function dependencies and guiding them to resolution. Help resolve the program’s hardest multi-functional bugs by translating ambiguous, multi-team symptoms into root-cause closure on areas such as HBM, power and thermal, high-speed I/O, and packaging. Steward the qualification playbook. When the playbook does not fit a situation, guide the mitigations and capture the lessons as reusable methodology for other SSG programs. Shape the program’s technical narrative by surfacing key risks, trade

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first. We are hiring a Senior Manager to lead this team in the US and partner closely with teams globally. Your work will sit on the critical path of every NVIDIA silicon program, and the bar you set for system integration is the bar we ship to! The two hardest, highest-leverage problems in this seat: Find critical silicon issues earlier — often before software is production-ready. Left-shifting post-silicon coverage is the highest-value thing System Integration can do. Standing up wide-area testing as a repeatable capability is a core part of the role. Keep programs on milestone when upstream dependencies slip. Validation plans collide with reality every program! The team needs new strategies, not just contingency plans, to keep moving when software, firmware, or methodology slip. You will design and run those strategies. What you’ll be doing: Plan and execute post-silicon feature integration, PVT validation, and wide-area testing across NVIDIA’s GPU, SoC, and CPU programs. Build wide-area and in-system test as a repeatable capability that shifts post-silicon coverage left, so issues surface before we are production-ready. Lead resolution of the most complex system-level issues, RMAs, and HW/SW interaction problems with creative workarounds and focused lab experimentation. Deve

NVIDIA's Silicon Co-design Group (SCG) sits at a rare intersection: we own the full product development lifecycle, from early architecture definition through silicon bringup to product release. Our ArchDev team is the hub for silicon and system-level feature development, driving tradeoff analysis, system integration, and POR alignment across the entire organization. If you want to see your work go from whiteboard to world-class silicon, this is where that happens. What You'll Be Doing: Architect and integrate system-level performance and power management features, controllers, and policies to optimize product efficiency across datacenter and client products . Build feature roadmaps to address low-power, low-noise, and performance-per-watt product needs through prototyping, use-case analysis, and cost/benefit trade-offs. Partner with architecture, ASIC, board/platform, software/firmware, and marketing teams to drive design decisions and debug complex issues. Track industry trends and market needs and translate them into forward-looking roadmaps that keep NVIDIA's products ahead of the curve. Lead debug efforts, develop workarounds, and support bringup , validation, manufacturing, and customer escalations. What We Need to See: <

SCG sits at the crossroads of design, architecture, marketing, and productization—owning the journey from the architecture stage through final product definition across Gaming, Datacenter, Automotive, and Embedded markets. As a System Verification CoDesign Engineer, you will work on system-level speed features, develop the verification collaterals and automation infrastructure to characterize and validate them, and lead debug of the complex silicon issues that stand between a program and on-time shipment. This is a hands-on role for an engineer who combines deep technical craft with the drive to compress cycle time using modern tooling—including AI—without losing rigor. What You’ll Be Doing: Collaborate cross-functionally with system architects, hardware, firmware/software, process/reliability, and operations teams to co-design system-level speed features and deliver industry-defining products. Understand system level behavior and speed reliability margins, bounding box constraints and identify solutions that optimize margins . Translate hardware features and architectural requirements into verification techniques that achieve full coverage across testing flows. Perform closed loop validation by correlat ing silicon behavior against timing simulation and design expectations; provide actionable feedback to improve future designs. Define, prototype, and refine pre- and post-silicon bring-up flows to ensure

Work Flexibility: Hybrid As a Portfolio Manager on Stryker’s Knee team , you will help shape the future of the Partial Knee portfolio by identifying customer needs, supporting new product development, and building the business case for commercialization. You’ll leverage research, market intelligence, and cross-functional collaboration to bring forward-thinking strategies to life and support our mission of moving patient lives. What you will do: Develop portfolio and product strategies by translating customer, patient, and market insights into compelling value propositions and growth opportunities. Leverage qualitative and quantitative market research, Voice of Customer (VOC), competitive intelligence, and third-party data to identify customer needs, industry trends, and market opportunities. Partner cross-functionally throughout the New Product Development (NPD) process , helping advance new products from concept through commercialization. Build financial business cases and ROI models to evaluate new product opportunities and support investment decisions. Develop market assessments, volume forecasts, and commercialization strategies grounded in market dynamics, customer insights, risk, and uncertainty. Partner with Product Marketing to develop go-to-market and product launch strategies for new products. Identify opportunities for customer acquisition, retention, market expansion, and portfolio growth , evaluating the financial tradeoffs associated with each. Partner with Clinical Affairs and Product Marketing to develop clinical evidence, publication, and messaging strategies that support portfolio objectives. Lead Product Lifecycle Ma

About the Team OpenAI Finance helps ensure the organization is set up for success in pursuit of its mission of ensuring that artificial general intelligence benefits all of humanity. Within Finance, the Revenue Accounting, Technical team partners with Product, Strategic Partnerships, Business Development, Growth, Legal, Deal Desk, GTM, Strategic Finance, Revenue Accounting, and Finance Systems to enable scalable, operationally sound monetization. We advise on commercial and contract design, establish clear accounting positions under ASC 606, and translate those conclusions into repeatable processes, systems, controls, and reporting. About the Role We’re looking for a Manager of Revenue Accounting, Technical to drive the end-to-end technical revenue and operational workstream for OpenAI’s strategic commercial deals—from early structuring and deal-desk review through contracting, launch, and ongoing governance. Reporting to the Head of Revenue Accounting, Technical, you will serve as a key revenue advisor for complex and non-standard strategic deals, translating commercial objectives into revenue models that are economically sound, accounting-compliant, and operationally executable. You will partner with senior team members on the most novel or high-risk matters across strategic collaborations, cloud marketplaces, platform and distribution deals, licensing and revenue-share models, joint go-to-market initiatives, research collaborations, and other emerging commercial structures. You will engage from the earliest stages of a deal to shape economics, pricing, commercial terms, contract language, and product design; define the supporting data, billing, settlement, reporting, systems, controls, and revenue-recognition model; and drive cross-functional readiness through launch. After launch, you will help govern amendments, monitor whether the model is operating as intended, resolve execution issues, and evolve the approach as the partnership or business model changes. Thi

About the role As a Pricing Strategist focused on GTM, you will help shape pricing strategy for B2B enterprise customers across our product portfolio. Working within Finance and partnering with GTM, Sales, and Product, you will focus on pricing analytics, price performance, and the effectiveness of credit programs while contributing to broader commercial strategy. In this role, you will Build regular pricing-performance reviews, analyze discounting and concessions, and turn findings into better pricing guidance. Develop commercial strategies and pricing programs for customer segments such as education, startups, and government. Define objectives and success measures for credit programs and promotions, and evaluate their return on investment. Translate segment goals and product pricing strategy into scalable pricing frameworks and commercial structures. Partner on strategic enterprise deals to align commercial proposals with sound deal economics and pricing strategy. You might thrive in this role if you Approach problems from first principles, identify root causes, and develop clear options for stakeholders. Work effectively through ambiguity and differing perspectives. Understand how sales organizations operate and collaborate well across GTM strategy, Finance, and Product. Bring relevant experience from consulting, strategy and operations, or pricing, particularly work involving analytical teams. Experience with pricing analytics, pricing frameworks, discounting guardrails, or new-product pricing is helpful, but a strictly pricing-specific background is not required. About OpenAI OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we mu

Job Details: Job Description: As a Senior Power and Performance (PnP) Engineer, you will be responsible for PnP product execution focused on measurements, analysis, and projections/estimates of Intel's unlaunched notebook and desktop products. Based on your technical knowledge of both Intel and the competition, you will help influence OEM customers, internal marketing teams, internal engineering teams, debug Intel silicon/platform on PnP issues, and be an integral part for Intel product launches. Core responsibilities to include following: Measure, analyze, and debug workloads to call out any power and/or performance gaps and close with internal engineering teams/architects Measure and analyze SoC/CPU and platform power on a rail by rail basis and debug any issues/gaps Align with other internal engineering teams and architects to ensure there is consensus on power and performance projections/estimates/measurements for both internal and external communication Guide, educate, and influence internal engineering teams, field account teams, and marketing teams on power and performance positioning of Intel products Create power and performance estimates on upcoming Intel products based on workloads to aid marketing decisions and help set internal KPI targets Own the publication of the Power Performance Guide (PPG) collateral to help guide OEM customers Bring up full test platform to enable both power and performance measurements including setup, calibration, and measurements. Qualifications: You mus

About the Team The Enterprise Marketing team helps the world’s largest organizations understand, adopt, and scale AI responsibly. We partner closely with Sales, Solutions, Product Marketing, Customer Success, Events, and executive leadership to create programs that accelerate strategic customer growth and strengthen OpenAI’s position as the leader in enterprise AI. Within Enterprise Marketing, the Field Marketing team is responsible for translating business priorities into high-impact customer engagement motions across industries, regions, and strategic accounts. We build and run programs that create pipeline, accelerate opportunities, deepen executive relationships, and bring OpenAI’s latest innovations directly to enterprise decision-makers. About the Role As an Enterprise Field Marketer, you will be a growth partner to Enterprise Sales, owning field marketing programs that create pipeline, accelerate strategic opportunities, and deepen relationships with priority enterprise accounts. Your focus will attach to the business’s most important needs at any given time, whether that means an industry motion, a regional priority, a strategic account, an executive engagement, or a new company-wide growth opportunity. You will own the full program lifecycle: translating sales priorities into field plans, identifying the right accounts and moments, executing high-quality customer programs, driving follow-up with sellers, and measuring business impact. This is a hands-on role for someone who can move from territory strategy to tactical execution quickly, with strong commercial judgment and high accountability for outcomes. This role is based in San Francisco, CA or New York City. We use a hybrid work model of 3 days in the office per week and offer relocation assistance. Travel is expected for customer events, executive programs, industry conferences, and internal planning moments. In this role, you will: Build and execute field marketing plans aligned to priority seller gro