Senior Advanced Analyst in United States

Job Details: Job Description: About the Role Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Senior Physical Design Engineer (CPU), you will play a key role in delivering high-performance, power-efficient silicon solutions. You will take ownership of blocks within the CPU core design, driving implementation from RTL to GDS and contributing to advanced physical design methodologies. What You’ll Do Key responsibilities will include but not limited to: Own physical design and implementation of CPU core blocks or subsystems Execute synthesis, floorplanning, place and route, and design closure Perform static timing analysis (STA), power analysis, and physical verification Drive convergence of timing, power, and area (PPA) metrics Debug and resolve complex design issues across multiple design stages Develop and optimize design flows and automation scripts Collaborate cross-functionally with RTL design, verification, clocking, and full-chip teams Contribute to improving design methodologies and best practices Provide guidance to junior engineers where applicable Behavioral traits that we are looking for: Strong problem-solving and analytical thinking Takes ownership and accountability for deliverables Collaborates effectively across multidisciplinary teams Communicates technical concepts clearly and concisely Prioritizes work effectively in a fast-paced environment Continuously learns and applies new tools and methodologies Why Join Us Work on cutting-edge CPU core designs that power client, server, IoT, and AI platforms used worldwide Be part of

Senior Low Observables (LO) Mission Systems Integration Engineer Company: The Boeing Company The Senior LO Mission Systems Integration Engineer will lead design, integration, analysis, test, and production activities for low observable materials, structures, apertures, sensors, and radomes for mission systems. The role requires strong technical leadership, independent execution of complex tasks, advanced use of computational electromagnetic (CEM) solvers, and the ability to produce and defend technical results with minimal oversight. Key Responsibilities Lead design, modeling, and analysis efforts for LO materials, coatings, structures, and integrated mission systems to meet signature reduction and performance requirements. Independently apply CEM solvers (e.g., FEKO, HFSS, CST, WIPL‑D, xFDTD, or equivalent) to model antennas, apertures, radomes, and LO treatments; perform design optimization and trade studies. Drive integration of LO treatments with mechanical, thermal, and sensor/antenna system constraints; identify and mitigate producibility, testability, and sustainment risks. Plan, execute, and oversee laboratory and field tests (anechoic chamber measurements, antenna/radome characterization, RCS measurements); lead data collection, reduction, and validation activities. Develop and validate predictive models, reconcile simulations with measurements, perform uncertainty quantification, and provide actionable recommendations to engineering and program leadership. Produce high-quality technical documentation: test plans, test reports, technical memoranda, design reviews, and customer briefings. Mentor and provide technical oversight to junior engineers and technicians; ensure adherence to engineering processes, qual

At NVIDIA, we push the boundaries of computing innovation. Our ASIC Verification Engineers focus on developing the world’s top SoCs and GPUs. Joining us as a Senior ASIC Verification Engineer - GPU means working on modern technology powering consumer graphics and AI applications. This position is ideal for those passionate about technology and eager to impact computing’s future. What you'll be doing: As a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading GPUs. You will be responsible for verifying the ASIC build, architecture, golden models, and micro-architecture using advanced verification methodologies such as UVM or equivalent. Understand the design and implementation of your unit/cluster/chip, define the verification scope, develop the verification infrastructure, and verify the correctness of the design. Collaborate with architects, designers, and pre- and post-silicon verification teams to accomplish your task. What we need to see: Bachelor's Degree in EE, CS, or CE or equivalent experience. 5+ years of relevant experience. Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies. Experience with design and verification tools (VCS or equivalent simulation tools, debug tools like Verdi, Indago, GDB). Expertise in System Verilog or similar HVL. Strong debugging and analytical skills. Perl and C/C++ programming language experience desirable. Strong communication skills and the ability & desire to work as a great teammate are huge pluses. Experience in crafting test bench environments for unit and system level verification. #LI-Hybrid Your base salary will be det

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The TD Electrical Device Characterization team pushes the boundaries of Micron’s memory technology. We explore device behavior, uncover insights through data, and collaborate across engineering teams to enable next-generation products. We are a hands-on team that values curiosity, precision, technical rigor, and collaboration. In this role, you will drive electrical characterization for advanced memory technologies and partner with device, process, and product teams to turn measurements into actionable technical insights. Your work will help guide technology development and shape the performance and reliability of future NAND, DRAM, and emerging memory products. Responsibilities: Lead electrical characterization for advanced memory devices Develop measurement methods, algorithms, and scalable characterization standards Automate data pipelines and analysis using Python, JSL, C/C&#43;&#43;, and dashboard tools Architect test setups and manage wafer probe and ATE test flows Investigate device behavior, identify root causes, and communicate technical findings Minimum Qualifications: <span style="color:#6

Experienced or Senior Digital Design Engineer Company: The Boeing Company Boeing Defense, Space & Security (BDS) seeks a Digital Design Engineer to join our team in Huntsville, AL and play a vital role in the Patriot Advanced Capability-3 (PAC-3) program, one of the world's most advanced air and missile defense systems. This is your opportunity to work in a dynamic environment where your skills will directly contribute to protecting critical assets and ensuring mission success. If you are passionate about defense technology and want to make a real impact, we want to hear from you! Position Responsibilities: Design high speed digital circuits and perform signal integrity analysis Focus on electronic systems and electrical design, simulation and verification/validation testing of high-speed printed circuit boards (PCB) throughout full product development cycle Providing design guidelines and support for system architecture design, board layout, product bring-up, debug, validation, and factory builds This position requires obtaining a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim U.S. secret clearance Pre Start and final U.S. secret clearance Post Start is required. Basic Qualifications (Required Skills/Experience): Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement 3 or more years of related work experience Experience in digital circuit design Preferred Qualificatio

Experienced or Senior Digital CCA Design Company: The Boeing Company Boeing Defense, Space & Security (BDS) seeks a Digital CCA Design Engineer who is a subject matter expert in high-speed digital circuit design , signal integrity analysis , and electrical design to join our time in Huntsville, AL. This position will p lay a vital role in the Patriot Advanced Capability-3 (PAC-3) program, one of the world's most advanced air and missile defense systems. This is your opportunity to work in a dynamic environment where your skills will directly contribute to protecting critical assets and ensuring mission success. If you are passionate about defense technology and want to make a real impact, we want to hear from you! Position Responsibilities: Focus on electrical design, simulation, verification, and validation testing of high-speed printed circuit board design and electronic system Lead product development cycles Collaborate with cross-functional teams, including other engineering disciplines Keeping current on related industry best practices and technological advancements This position requires obtaining a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim U.S. secret clearance Pre Start and final U.S. secret clearance Post Start is required. Basic Qualifications (Required Skills/Experience): Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement. 3 or more years of related experien

Work Flexibility: Onsite Schedule: Mon – Fri 6:00am - 2:30pm, OT as needed What you will do: As a Senior Materials Inventory Coordinator, you will be responsible for material coordination and inventory control across production, quality, and logistics to ensure accurate records, timely material availability, and efficient material flow. This role focuses on executing established processes, identifying improvement opportunities, upholding quality and safety standards, and collaborating with cross-functional teams to support daily operations. Coordinate and optimize the flow of raw materials, components, and finished goods to ensure uninterrupted production and efficient inventory movement. Own inventory accuracy within ERP/WMS systems, performing complex transactions, cycle counts, and detailed discrepancy investigations. Collaborate cross-functionally with production, quality, planning, and logistics to ensure timely material availability and accurate staging for work orders. Serve as a subject matter expert and escalation point for complex material and inventory issues, driving root cause analysis and resolution. Execute and validate advanced inventory processes, including receipts, transfers, adjustments, and work order transactions, ensuring compliance with established controls. Drive continuous improvement efforts to enhance inventory accuracy, streamline material flow, and improve operational efficiency. Ensure compliance with material identification, labeling, and traceability requirements, supporting audit readiness and regulatory standards. Lead by example in maintaining a safe, organized work environment while supporting audits, physical inventories, and best practice adoption. What you need:

As a Senior Technical Solutions Consultant , you will be the principal technical liaison between our product, sales, and customer success teams. You will provide tailored solutions for clients in the commercial real estate sector, specifically focusing on the complex VTS Activate product landscape (including Activate, Activate Workplace, Activate Multifamily, CBRE Host, and CBRE Host Building) . Your unique combination of property management experience and deep technical proficiency will help ensure that our clients maximize the value of our software. ** Please note that this opportunity is located in New York, NY, and requires this hire to work from our office 4 days a week. ** What Makes This Job Awesome? Act as the definitive subject matter expert (SME) and technical leader for the VTS Activate suite's integration landscape and partnerships, both internally and externally (e.g., Braxos, Kastle, CCure, AMAG, etc.). Design and deliver advanced, in-depth technical demonstrations for prospects and clients, specifically showcasing how the VTS Activate product suite solves specific challenges. Provide advanced technical support during the sales process, addressing complex questions and concerns about system integrations and core functionalities, serving as the technical closer for Activate deals. Provide support during the sales process for qualifying opportunities with hardware requirement and implementation. Provide handover details to cross-functional stakeholders to ensure smooth implementations. Own the solution reporting process for VTS Activate deals, including documenting deal journals and synthesizing won/loss reasons. This reporting provides critical intelligence for the Product team (feature gaps), the Sales team (competitive analysis), and the Executive team (market/product trends). Lead knowledge transfer and cross-functional upskilling initiatives for the Sales, Customer Success, and Services teams. This involves supporting the creation of documenta

NVIDIA is seeking a Senior Firmware Engineer to join our CSP Engagements team, focusing on system software for Datacenter products such as GB200. This role combines deep technical expertise in embedded firmware development with customer-facing responsibilities to enable cloud service providers with next-generation computing platforms. You will work at the intersection of hardware and software, driving technical solutions from concept through deployment. What you will be doing: Design and develop firmware solutions for manageability and observability of data center servers. Actively participate in hardware bring-up activities, OOB firmware development, protocol stacks (Redfish, PLDM, MCTP, NSM) and hardware-software co-design for Cloud Service Provider deployments. Debug and troubleshoot NVIDIA GPU firmware issues, power management, performance, and thermal control problems for data center deployments, providing active support to CSPs. Partner directly with CSPs to deliver technical solutions, co-develop & co-debug features and optimizations, and provide support during new product introductions. Perform advanced system debugging, root cause analysis, and performance optimization for large-scale data center environments. Collaborate with AE, FAE, and Solution Architect teams to deliver integrated customer solutions and technical documentation. What we need to see: Deep expertise in data center server architectures, HPC systems, and hardware-software co-design. Deep expertise in embedded firmware, server management controllers, and hardware bring-up with proven track record of shipping production BMC solutions Strong knowledge of DMTF protocols (Redfish, IPMI, PLDM, MCTP, SPDM), telemetry frameworks, and out-of-band management architectures Expert-level skills in C/C&

Ground Systems Integration Engineer (Experienced or Senior Level) Company: The Boeing Company Boeing Defense, Space & Security (BDS) is seeking a Ground Systems Integration Engineer (Experienced or Senior Level) to support an Air Dominance Fixed Wing Proprietary Program in Berkeley, MO . Step into a fast-paced, cutting-edge program where your expertise will drive the design, integration, and testing of advanced, cloud-based systems that empower mission planning, debrief, and tactical Command & Control (C2) solutions for fixed-wing platforms. As a key contributor, you will support the development, analysis, integration, and testing of innovative engineering solutions for critical Ground System capabilities, including but not limited to: Mission Planning and Debrief Command and Control Systems Network and Communication Architectures Situational Awareness Enhancements You will take ownership of developing prioritized mission systems digital threads, ensuring seamless support for ground systems from initial design through to final delivery. You will work with a high-performing, cross-functional team in an agile environment, driving next-generation capabilities from design through delivery. This role offers the chance to innovate with open-architecture, model-based designs while collaborating across disciplines to support critical defense missions. If you’re passionate about advancing mission-critical systems and thrive in a collaborative, fast-moving environment, this is your opportunity to make a significant impact. Why Join Us? Impactful Work: Be part of a team that plays a crucial role in

Job Details: Job Description: The Thin Films Senior Process Engineer will support PVD, CVD, and ALD technologies for dielectric and metal thin-film deposition in a high-volume manufacturing environment. Key Responsibilities Apply advanced expertise in thin-film deposition processes to drive continuous improvement in process performance, sustainment, and technology development. Collaborate with upstream and downstream partners to deliver manufacturing improvements through strong cross-functional engagement and stakeholder management. Own manufacturing processes and/or equipment, ensuring achievement of key performance indicators (KPIs) including safety, quality, cost, productivity, defect reduction, and yield improvement. Develop and execute strategic plans for complex projects, coordinating timelines and dependencies across multiple teams and initiatives. Support manufacturing capacity expansion and technology transfer activities to enable successful ramp-to-volume production. Partner with equipment vendors and cross-functional stakeholders to troubleshoot technical challenges, improve tool performance, and enhance operational efficiency. Lead process development initiatives that support current and next-generation high-volume manufacturing technologies. Design and optimize excursion prevention and detection systems to strengthen process control and minimize manufacturing risk. Lead equipment installation, conversion, qualification, and readiness activities during factory ramps, ensuring all tools are deployed safely, on schedule, and in compliance with quality and manufacturing standards. Drive root cause analysis and implement corrective actions to resolve process and equipment-related issues while improving overall manufacturing stability and performance. <p st

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer with a strong background in static timing analysis (STA). In this role, you will help converge multi-million-gate designs on advanced process nodes and partner with cross-functional teams through final signoff and tapeout. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A physical design engineer with 8+ years of experience in STA, timing closure, and advanced-node design implementation. Experienced with timing flows, constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding, and final signoff. Skilled in writing and debugging SDC constraints, creating ECOs, developing closure strategies, and analyzing worst-case corners. A strong collaborator and communicator who can drive results across distributed, cross-functional engineering teams. What We Need Drive timing convergence across blocks, partitions, sections, and top-level designs; generate and validate timing models and publish results. Analyze timing violations, develop and propagate fixes, debug timing-flow issues, and

About the Team OpenAI’s Hardware organization develops system and infrastructure solutions designed for the unique demands of advanced AI workloads. We work closely with architecture, infrastructure, and vendor teams to evaluate system performance and guide critical design decisions. Our team focuses on building and applying performance modeling frameworks to understand system behavior, quantify tradeoffs, and support next-generation infrastructure design. About the Role We are seeking an Performance Modeling Engineer to support the development and application of modeling tools used to evaluate AI system performance and inform architectural decisions. In this role, you will partner closely with Senior Performance Modeling Engineers and the Performance Modeling Lead to analyze system behavior, run simulations and analytical models, and help evaluate tradeoffs across compute, memory, networking, and storage. You will contribute to building modeling frameworks while developing a strong foundation in system architecture and AI infrastructure. This role is ideal for early-career engineers with 1–2 years of experience in software engineering, systems analysis, or performance modeling who are excited to grow in large-scale infrastructure and hardware/software systems. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance. Key Responsibilities Support the development and maintenance of performance modeling tools and frameworks Assist in building models to evaluate system behavior across compute, memory, networking, and interconnect subsystems Help analyze distributed system scaling behavior and identify performance bottlenecks Run simulations and analytical models to support architecture and infrastructure decisions Partner with senior engineers to evaluate design tradeoffs across hardware and system components Interpret modeling outputs and help translate findings into clear recommendations Vali

About the Team OpenAI, in close collaboration with our capital partners, is building the world’s most advanced AI infrastructure ecosystem. Our Industrial Compute organization develops and deploys large-scale AI campuses designed to support the next generation of frontier model training and inference workloads. The Hardware Operations team is responsible for ensuring the reliability, availability, and lifecycle health of OpenAI’s compute infrastructure. We partner closely with Data Center Operations, Fleet Health Engineering, Manufacturing, Network Infrastructure, Capacity Planning, and our infrastructure partners to maintain world-class operational performance across rapidly expanding AI environments. As we scale globally, we are building the operational frameworks, reliability standards, and sustaining engineering practices required to support thousands of GPUs and servers across multiple campuses. About the Role We are seeking a Datacenter Hardware Technician Lead to serve as the senior on-site technical authority for hardware reliability and fleet health at one of OpenAI’s flagship AI campuses. This role operates at the intersection of hardware operations, sustaining engineering, and fleet reliability. You will partner closely with Cloud Service Provider operations teams, OpenAI fleet-health engineers, hardware engineering teams, and OEM vendors to identify, diagnose, and resolve hardware issues affecting production systems. Beyond day-to-day operational support, you will drive root cause investigations, reliability improvement initiatives, lifecycle management programs, and operational readiness efforts. You will help establish hardware maintenance standards, operational procedures, and best practices that scale across future OpenAI infrastructure deployments. The ideal candidate combines deep hands-on datacenter hardware expertise with strong troubleshooting, failure analysis, and cross-functional leadership skills. Candidates must be able to sit onsite at our

About the Team OpenAI’s Industrial Compute team is building and productizing infrastructure capabilities that help organizations deploy and operate advanced AI systems at scale. The team works across AI hardware, systems engineering, physical infrastructure, and customer delivery to turn emerging technologies into reliable, repeatable infrastructure solutions. Our work sits at the intersection of technical strategy, product development, engineering, and deployment. We partner closely with customers and internal engineering teams to solve complex infrastructure challenges spanning compute, power, cooling, controls, and facility efficiency. About the Role We are seeking a senior, hands-on Data Center Infrastructure Architect to develop and optimize the physical infrastructure required for large-scale AI deployments. This is a broad technical role spanning data center architecture, electrical and mechanical systems, high-density compute, controls, telemetry, and digital modeling. You will use simulation, operational data, and digital-twin approaches to evaluate infrastructure designs, identify system-level constraints, and improve efficiency, reliability, cost, and speed of deployment. The ideal candidate can move fluidly between first-principles analysis, facility and equipment design, computational modeling, engineering review, and real-world implementation. You should be comfortable working across disciplines rather than operating solely within electrical, mechanical, or software boundaries. Key Responsibilities Define system-level architectures for high-density AI data centers across power, cooling, IT equipment, controls, and facility infrastructure. Develop digital twins and other computational models that represent the behavior of data center systems under changing workloads, environmental conditions, equipment configurations, and failure scenarios. Use design and operational data to identify constraints, improve PUE and related efficiency metrics, and optimize