Software Engineer Product Security Data Platforms Salary India in United States

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a senior High Speed Interconnect / Signal Integrity Engineer to design and validate high-bandwidth links for large-scale AI systems. You will define, model, and qualify interconnect solutions across copper and optical technologies for next-generation AI inference and training clusters. This role is on-site in Santa Clara, CA, Austin, TX, or Toronto, Canada. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting Who You Are An experienced electrical engineer with a Bachelor’s or Master’s in Electrical Engineering. 5+ years working on high-speed communications (100G–1.6T), including signal integrity, channels, and links. Comfortable building and owning link and channel budgets and making clear tradeoffs between reach, loss, BER, and margin. Hands-on with SI tools and lab equipment such as Keysight ADS, VNAs, TDRs, BERTs, and protocol analyzers. Familiar with cable specification and testing, as well as accelerated life testing, mating life, and failure analysis. Able to collaborate across hardware, systems, and manufacturing teams; manufacturing/DFM/DTM experience is a plus. What We Need Define and specify high-speed interconnect architectures

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which the GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As a Developer Technology Engineer you will be at the forefront of innovation, working with leading industry partners and exciting OSS projects to accelerate RTX & DGX SoC performance for agentic use. This role offers an outstanding opportunity to collaborate with world-class talent and make a significant contribution to the next era of enterprise and consumer AI. What you'll be doing: Own key engagements with our fast-paced developer ecosystem partners, optimizing their applications to deliver outstanding end-to-end performance on RTX and DGX SoCs. Take ownership of performance optimization for compute-intensive CPU, AI, and 3D graphics workloads, working with domain experts to identify bottlenecks and implement effective solutions. Work across system software, GPU driver, architecture, and NVIDIA Research teams to influence next-generation, high-performance SoC platforms by bringing real-world workflows and actionable insights from partner and customer needs. Provide technical guidance and mentorship to junior engineers while contributing to an inclusive and high-performing team environment. What we need to see: BS or MS degree in Computer Science, Engineering, Mathematics or related degree (or equivalent experience) 5+ years of respective work experience as software developer Proficiency in C/C++, Python, software

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Would you like to work in one of the most complex Fab environments in the world? As an industrial engineering intern in our research and development factory you will work on projects that further optimize our very automated factory. This role will provide exposure to larger data sets than you have ever worked with and will challenge your data management skills. Not only will this role significantly grow your skills but will also provide exceptional value to the organization on a real issue in our factory! Responsibilities: Identify key performance indicators for R&D program success. Use large data sources to extract and analyze planning data. Build reporting in Tableau and other systems to convey data to program teams. Construct infographics that display key information in easy-to-understand formats. Leveraging AI tools and find new ways to apply AI in the workplace. Minimum Qualifications: Working towards completion of a Bachelor’s or Master’s degree in the following areas: industrial engineering, manufacturing engineering, supply chain, Operations or other related discipline with expected graduation after this internship timeframe Must be a current student, and cannot graduate prior to September 2027. Ability to code in SQL, Python or similar to execute data extraction. Effective with Excel, Tableau or other data management and visualization software. Preferred Qualifications: Skille

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role summary We are seeking a Networking Operating System Firmware Engineer to help bootstrap and scale the switching layer of our AI supercomputers. In this role, you will build and maintain custom NOS images from scratch, using open source components from SONiC, SAI, FRR, and related networking stacks while working across the Linux kernel, switch ASIC SAI/SDKs, platform drivers, control-plane services, and orchestration layers. This is a software engineering role that requires a deep understanding of networking, NOS internals, switch hardware, and production systems. You will design, implement, test, and debug production NOS software across platform drivers, routing and control-plane state, ASIC programming, observability, and fleet integration. The engineer in this role should be able to work through ambiguous, open-ended technical problems and drive feature development across software, hardware, and vendor boundaries. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will Design, develop, and maintain custom NOS images for large-scale AI fabrics, using open source components from SONiC, FRR, and related networking stacks. Integrate, build and configure Linux kernel components, device drivers, switch ASIC SDKs, and SAI layers. Bring up new switch platforms, including thermal and fan control, power monitoring, transceiver management, watchdogs, OSFP CMIS, L

About the Team OpenAI’s Infrastructure organization builds and evaluates the systems that power advanced AI workloads. We work closely with hardware, modeling, and architecture teams to ensure that new platforms deliver real-world performance aligned with workload needs. Our team focuses on understanding workload behavior across evolving hardware platforms—bridging the gap between theoretical capability and observed system performance. About the Role We are seeking a Workload Porting & Performance Engineer to evaluate new hardware platforms by porting benchmarks and real-world workloads, analyzing performance, and identifying system bottlenecks. In this role, you will bring up workloads on new systems, characterize performance behavior, and adapt workloads to better utilize hardware capabilities. You will play a critical role in validating new platforms and ensuring that performance aligns with expectations across compute, memory, and networking subsystems. This role requires strong hands-on experience with performance analysis, workload optimization, and system-level debugging across hardware and software boundaries. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance. Key Responsibilities Port and enable benchmarks and real-world workloads on new hardware platforms. Evaluate system performance across compute, memory, storage, and networking subsystems. Identify and analyze performance bottlenecks and inefficiencies. Adapt and optimize workloads to better utilize hardware capabilities. Develop and run performance experiments and profiling workflows. Compare expected vs. observed performance and provide feedback to: hardware architecture teams performance modeling teams system and software engineers. Debug issues across the stack, including software, runtime, and hardware interactions. Provide actionable insights to guide platform readiness and deployment decisions. Qualifications E

At Snowflake, we are powering the era of the agentic enterprise. To usher in this new era, we seek AI-native thinkers across every function who are energized by the opportunity to reinvent how they work. You don’t just use tools; you possess an innate curiosity, treating AI as a high-trust collaborator that is core to how you solve problems and accelerate your impact. We look for low-ego individuals who thrive in dynamic and fast-moving environments and move with an experimental mindset — who rapidly test emerging capabilities to discover simpler, more powerful ways to deliver results. At Snowflake, your role isn't just to execute a function, but to help redefine the future of how work gets done. As a Senior Forward Deployed Engineer (FDE), you will be embedded with customers to lead the modernization of their data and application ecosystem using the Snowflake AI Data Cloud. You will especially focus on modernizing their Spark and Data Engineering focused workloads. You will partner closely with clients to understand their business challenges and design, build, and implement cutting-edge data solutions on Snowflake. Your role is crucial in enabling customers to harness the full potential of their data, driving insights, and powering AI initiatives. You'll act as a trusted technical advisor, ensuring customers achieve significant business value and success with Snowflake. WHAT YOU WILL BE RESPONSIBLE FOR: Software Development : Design, build, and deploy robust software systems, tooling, and automation required to support customer solutions on Snowflake. Create comprehensive documentation for developed solutions, technical configurations, and best practices. Data Engineering & Platform Implementation : Design and implement scalable data pipelines and modern data architectures on Snowflake. Ensure data quality, integrity, and efficient processing within the customer's modern data environment. Performance Optimization & Best Practices : Analyze and optimize data

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team and lead the front-end RTL physical implementation team. Drive CAD flows on multiple process technologies while working closely with core micro-architects to refine CPU core configurations and optimizing PPA. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, RTL and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An expert in physical design practices used to optimize PPA Experienced in high-performance physical design. Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis. Skilled in synthesis, place and route tools including flows and physical design methodology. Background in CPU micro-architecture. What We Need Own front‑end physical implementation and PPA definition for a high‑performance RISC‑V CPU and CPU subsystem Work closely with microarchitects and RTL designers to “make the IP better” by optimizing frequency, power, and area

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Sr. Staff Design Verification Engineer to lead end-to-end verification efforts for our advanced CPU and AI compute platforms. This role is ideal for seasoned engineers with deep expertise in CPU verification who excel at driving complex test plans to closure, mentoring teams, and leveraging modern AI tools to accelerate innovation. This role is hybrid, based out of Boston, Toronto, Ottawa or Santa Clara. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Proven track record leading end-to-end CPU verification across processor cores, caches, interconnects, interrupts, MMU/IOMMU, and cache coherency protocols, with multi-chip and emulation experience a plus. Expert in creating comprehensive test plans and building simulation testbenches using SV-UVM, C/DPI, and Cocotb. Skilled in managing high-volume regression execution, complex failure triage, and driving test plans and coverage metrics to closure. Experienced leader and mentor dedicated to guiding junior engineers and fostering verification best practices across teams. Proficient in leveraging modern AI tools like Copilot, Cursor, Claude, Gemini, and ChatGPT to optimize ver

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Curious about how cutting-edge hardware actually comes to life? We're looking for someone who’s excited to dive into the core of next-gen systems and help make them real. In this role, you’ll validate high-speed interfaces, solve complex system-level puzzles, and collaborate across teams to shape the future of AI/ML computing. If firmware, hardware, and hands-on debugging sound like your kind of fun — let’s chat! This role is hybrid and based in Vancouver, Canada. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You love bringing hardware to life and enjoy the thrill of solving tricky problems across the hardware–firmware boundary. You’re hands-on in the lab and comfortable with tools like oscilloscopes, protocol analyzers, and JTAG — digging deep doesn’t scare you. You’re comfortable jumping into unfamiliar problems and figuring things out — whether it’s in the lab or in firmware. You’re curious, collaborative, and excited to work on technology that pushes the boundaries of performance. What We Need Someone to take the lead in validating our next-gen PCIe interfaces — from controller to PHY, and everything in between. A strong co

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Design Verification Engineer to contribute to the unit-level verification of our RISC-V CPU front end—including instruction fetch, branch prediction, and surrounding fetch control structures. As a key individual contributor within our front-end DV team, you will focus on building testbenches, generating stimulus, and developing checkers for complex microarchitectural scenarios. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Front-End Experience: Solid background verifying CPU front-end blocks—such as instruction fetch, branch predictors (BTB, TAGE, RAS), instruction caches/TLBs, or decode—using SystemVerilog, UVM, and C++. Unit-Level Focus: Hands-on experience building clean, controllable unit testbench environments with precise stimulus and checking. Reusable Design: Pragmatic approach to building transactors, predictors, and scoreboards that can be reused across verification levels. Collaborative Problem Solver: Comfortable working alongside RTL designers to trace and fix misspeculation, redirect, and edge-case fetch bugs. What We Need Unit-Level Verifica

Sr. Engineer - Testing & Quality Assurance S Ready to turn bold ideas into real-world impact? At Genpact, we don’t just adapt to change, we lead it. AI and digital innovation are transforming the way businesses work, and we’re at the forefront of it. Genpact’s AI Gigafactory , our industry-first accelerator, exemplifies how we scale advanced technology solutions to help global enterprises work smarter, grow faster, and transform at scale. Whether tackling complex challenges through large-scale models or agentic AI , our breakthrough solutions tackle companies’ most complex challenges. If you thrive in a fast-moving, innovation-driven environment, love building and deploying cutting-edge AI solutions, and want to push the boundaries of what’s possible, this is your moment. Genpact (NYSE: G) is an agentic and advanced technology solutions company. We leverage process intelligence and artificial intelligence to deliver measurable outcomes. With a strong partner ecosystem and decades of client trust, we provide innovative solutions that transform how businesses run. Powered by a team with an active learning mindset and client centricity at its core, we deliver lasting value for the world’s leading enterprises. Get to know us at genpact.com and on LinkedIn , YouTube , X , and Facebook . Job Description • Develop and execute test cases to identify software defects; • Collaborate w

Job Details: Job Description: The Role As a Cloud Application Development Engineer within Intel Manufacturing Foundry Cloud Services (imFCS) , you will design, develop, deploy, and support cloud-native applications that power semiconductor manufacturing, engineering automation, and AI-driven factory operations. You will build scalable, secure, and resilient platforms that improve engineering productivity, enable advanced analytics, and accelerate Intel Foundry's digital transformation. Key Responsibilities Develop and maintain cloud-native applications and services supporting manufacturing and engineering workflows. Support 24x7 manufacturing operations through on-call rotations, incident response, and root-cause analysis. Design and implement scalable microservices, APIs, and containerization systems utilizing Kubernetes orchestrator and cloud native applications. Architect secure cloud solutions spanning application, data, networking, identity, and observability domains. Build and maintain CI/CD pipelines, Infrastructure-as-Code, and DevOps automation. Provide technical leadership for contractor and partner development teams across multiple geographic regions, driving architecture, implementation, and operational excellence for cloud-native solutions. Collaborate with manufacturing, engineering, and software teams to deliv

About the Team The Finance Platform & Technology team builds and scales the systems and data architecture that power OpenAI’s core financial operations. We enable business agility, compliance, and operational excellence across procure-to-pay, quote-to-cash, supply chain, financial planning, and asset management. We partner with Procurement, Accounting, Tax, Legal, Security, Data, and Engineering to modernize workflows through thoughtful platform design, reliable integrations, scalable automation, and trusted data. About the Role As a Business Systems Lead for Procure-to-Pay, you will be a hands-on engineer who designs, builds, and operates the integrations and first-party applications that power OpenAI’s procurement workflows. You will translate business needs into secure, scalable software, APIs, data flows, and automation across Oracle Fusion, Zip, and connected platforms. You will build the future of buying at OpenAI using OpenAI’s own technology, from guided intake and approval experiences to supplier onboarding, purchasing, receiving, invoicing, and downstream financial data flows. You will own the technical roadmap and support model for these capabilities, improving today’s platforms while deciding where to integrate, configure, or build as OpenAI scales. Your core strength will be software and integration engineering. You will personally write code, troubleshoot cross-system failures, and take solutions through testing, deployment, and production support. You will also make targeted functional configurations in procurement platforms and partner with functional specialists on deeper process and module design. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Design, build, and operate integrations across Oracle Fusion, Zip, and connected systems using APIs, events, messaging, and batch interfaces where appropriate. Build first-party

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary We are seeking a Staff Hardware Engineer to provide advanced operational, diagnostic, and engineering support for Graphcore’s Arm-based hardware platforms across lab and data center environments. This role focuses on supporting hardware bring-up, validation, and troubleshooting of complex AI compute platforms, including server blades, racks, and rack-scale infrastructure. The successful candidate will collaborate closely with engineering, platform, and data center teams to ensure the reliability and performance of next-generation AI systems. The Team The Systems Engineering and Hardware Engineering teams are responsible for enabling the bring-up, validation, and operational reliability of Graphcore’s AI infrastructure platforms. The team works closely with server engineering, firmware teams, platform architects, and data center operations to support the development, testing, and deployment of next-generation AI compute systems. This collaborative environment enables rapid problem-solving and continuous improvement of Graphcore’s hardware platforms from early development through production deployment.

NVIDIA is seeking a Senior System Architect: Heterogeneous EDA Systems to solve a complex challenge in accelerated computing: Failure Attribution at Scale. As EDA or equivalent experience workloads scale across thousands of heterogeneous nodes, a single failure can cause massive resource waste. We need an engineer to develop and build an automated framework. This framework will ingest telemetry from CPU and GPU clusters to identify the root cause of job failures in real-time. It will distinguish between hardware faults, infrastructure instability, and software defects. What you'll be doing: Architect Failure Attribution Frameworks: Build a scalable "flight recorder" for EDA jobs that captures high-fidelity state across the CPU, GPU, and Fabric at the moment of failure. Build automated diagnostics that correlate GPU XID errors, PCIe bus failures, and CUDA memory exceptions. Connect these errors with system-level events such as OOM kills or NUMA-related hangs. Distributed Logging & Tracing: Implement low-overhead tracing mechanisms (using tracing tools or custom agents) that provide access to job execution across multi-node Slurm or Kubernetes clusters. Root Cause Automation: Develop heuristics and models based on machine learning to classify failures as "Hardware Fault," "Software Bug," or "Environment Issue." This reduces the Mean Time to Identify (MTTI) for R&D teams. Resiliency Engineering: Work closely with hardware and infrastructure teams to define "signals of impending failure," enabling proactive job migration or check-pointing before a crash occurs. What we need to see: Distributed Systems Mastery: BS, MS, or PhD in Computer Science or Electrical Engineering (or equivalent experience) with 6+ years in systems programming. Experience building automated