Solution Architecture Platforms Manager in United States

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Engineer at Micron’s HBM New Product Validation team in Boise, ID you will be a senior technical guide responsible for validation strategy and readiness for future-generation High Bandwidth Memory (HBM) products. You will apply deep expertise in complex RAM and high-bandwidth memory architecture and building to establish architecture validation strategies. You will impact decisions that improve validation observability and debug efficiency . You will lead investigations of complex architecture, building , and silicon issues from pre-silicon simulation through post-silicon characterization. You will partner across Design Engineering, Design Validation, Product Engineering, Systems teams, and will develop and promote AI-enabled validation methodologies that improve efficiency, quality, and scalability. Responsibilities: Define architecture-aware validation strategies and coverage direction for future-generation HBM products. Drive validation readiness for next-generation products by preparing strategies, test environments, and execution plans before first silicon, reducing risk, accelerating issue resolution, and preventing late-stage surprises. Evaluate new DRAM/HBM architectural features and define validation requirements and testability needs before DBR. <span style="color:#

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The HBM Design Technology Package Co-Optimization (DTPCO) organization is seeking a Staff Engineer! Lead the design and development of test vehicles that enable technology learning and risk reduction for future HBM products! This role serves as a key technical contributor within DTPCO, partnering closely with Architecture, Design, Layout, Product Engineering, Reliability, and Advanced Packaging teams to translate emerging product requirements and technology challenges into actionable test vehicle solutions. You will apply expertise in semiconductor design, physical implementation, silicon characterization, and advanced packaging technologies to define test structures, develop validation strategies, and generate data that drives product decisions across future HBM generations. Unlike a traditional product role centered on ownership of product blocks, this position emphasizes enabling learning in development and engineering. It does so by developing representative test vehicles and characterization structures. Key Responsibilities Serve as a technical lead for HBM test vehicle design and structure development within DTPCO. Partner with HBM product, technology and reliability team. Define and implement test structures targeting key learning areas such as package interaction and reliability Drive test vehicle content definition, structure specifications, measurement requirements, and validation objectives. Analyze silicon characterization and qualification results to identify optimization opportunit

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Design Technology Co-Optimization (DTCO) team works at the intersection of process technology, standard cell architecture, and design implementation to optimize power, performance, and area (PPA) for advanced memory products. The team collaborates closely with standard cell library, RTL, and physical design engineers to evaluate design tradeoffs and develop methodologies that improve silicon outcomes. As a DTCO Intern, you will gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level. You will use industry-standard place-and-route tools and AI-enabled automation techniques to implement, benchmark, and optimize logic blocks while developing practical skills in physical design, timing closure, and design analysis. Responsibilities Implement standard cell logic blocks using industry-standard physical design tools, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization activities focused on PPA assessment. Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations, identifying opportunities for improvement. Perform static timing analysis (STA), investigate setup and hold timing violations, and support timing closure activities. Execute physical verification checks, including DRC, LVS, and IR-drop analysis, and assist with resolving design issues. Leverage Generative AI, AI Assistants, and Agentic AI solutions to automate data collection, reporting, comparison, and w

About us Graphcore is one of the world’s leading innovators in artificial intelligence compute. We are developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and support the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of a family of companies responsible for some of the world’s most transformative technologies. Together, we share a bold vision to enable advanced artificial intelligence and ensure its benefits are accessible to everyone. Graphcore brings together AI researchers, silicon designers, software engineers and systems architects to solve complex technical challenges and deliver innovative computing solutions. Job Summary The Principal Electrical Engineer will be a technical authority within Data Center Engineering, leading the architecture and delivery of safe, resilient and scalable electrical infrastructure for high-density AI computing environments. Working with internal teams, data center developers, utilities, consultants and equipment partners, this role will guide projects from early technical studies through design, construction, commissioning, operation and lifecycle improvement. The successful candidate must reside in, or be willing to relocate to, Austin, Texas. Approximately 10% travel may be required. The Team The Data Center Engineering team is responsible for defining and enabling the infrastructure needed to deploy and operate Graphcore’s computing systems at scale. The team works across electrical, mechanical, thermal, controls, systems and operational disciplines, collaborating with external engineering and construction partners to deliver reliable, efficient and maintainable data center environments. Responsibilities and Duties Act as the technical authority for electrical engineering across data center infrastructure projects, from the utility or on-site power source through to the IT rack. Lead electrical archit

Power and Performance Validation Engineer About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations. This role requires strong technical expertise and collaboration across multiple engineering disciplines to deliver robust validation methodologies, scalable automation frameworks and actionable performance insights. The Team The Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems. The team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debug compl

Staff -Power and Performance Validation Engineer About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations. This role requires strong technical expertise and collaboration across multiple engineering disciplines to deliver robust validation methodologies, scalable automation frameworks and actionable performance insights. The Team The Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems. The team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debu

About the Team The mission of the Applied AI Engineering team is to enable the secure and impactful implementation of GenAI solutions. We serve as technical thought partners and trusted advisors to our clients, ideating high-value use cases and providing the hands-on guidance necessary to drive projects into production. In this role within the Government team, you will empower agencies to evolve their operations through automated content synthesis, advanced search capabilities, and bespoke applications leveraging our latest foundational technologies and models. About the Role We are looking for a driven solutions leader with a product mindset to partner with our public sector customers and ensure they achieve tangible value with GenAI. You will pair with government agencies (federal, state, and local), policymakers, and other public institutions to establish a GenAI strategy and identify the highest value applications. You’ll then partner with their technical teams, subject matter experts, systems integrators, and implementation partners to move from prototype through production. You’ll take a holistic view of their needs and design an architecture using the OpenAI API and other services to maximize customer value. You will collaborate closely with Sales, Solutions Engineering, Global Affairs, Applied Research, and Product teams. This role is based in Washington, DC. We offer relocation support to new employees. In this role, you will: Deeply embed with our most sophisticated public sector customers as the technical lead, serving as their technical thought partner to ideate and build novel applications on our API and other OpenAI foundational technologies like Codex. Work with senior customer stakeholders to identify the best applications of GenAI in their industry and to build/qualify a comprehensive backlog to support their AI roadmap. Intervene directly to accelerate customer time to value through building hands-on prototypes and/or by delivering impactful strate

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Sr Design Engineer, you will work on design, simulation, and validation of next ‑ generation High ‑ Bandwidth Memory (HBM) architectures and circuit blocks. HBM requires advanced DRAM design knowledge combined with deep understanding of 3D stacked architecture, TSV signaling, wide I/O interfaces, PHY timing, power integrity, and system co ‑ optimization with GPUs/accelerators. This role sits at the intersection of DRAM design and high ‑ performance computing, enabling future AI/ML, HPC, and advanced graphics products. In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a Senior Analog Design Engineer to join our High Bandwidth Memory (HBM) team. This role is responsible for the architecture, design, simulation, and silicon bring ‑ up of high ‑ performance analog and mixed ‑ signal circuits used in HBM PHYs and supporting infrastructure. The ideal candidate has deep expertise in high ‑ speed I/O, clocking, power management, and advanced ‑ node analog design, and has successfully delivered silicon to production. Responsibilities will include, but are not limited to: Design and own critical HBM analog circuits, including: High ‑ speed transmitters and receivers Clock generation and distribution (PLLs, DLLs, CDRs) SerDes ‑ related analog blocks Biasing, reference, and calibration circuits </

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about driving innovation for next-generation memory solutions powering AI/ML and high-performance computing systems. As a Director of HBM RTL Design and Integration, you will lead a team responsible for the design, integration, and delivery of next-generation HBM SoC logic die, with a strong focus on RTL development and IP integration. You will drive technical strategy and execution across multiple product generations, working closely with architecture, verification, physical design, firmware, and product engineering teams. Key Responsibilities Lead SoC RTL design and integration for HBM logic die, including subsystem partitioning, IP integration, and SoC-level design convergence. Drive translation of architectural and micro-architectural specifications into robust, high-quality RTL implementations across multiple teams. Oversee SoC integration aspects, including clocking, reset, power intent, configuration infrastructure, and system-level design correctness. Establish design methodologies and best practices to improve quality, reuse, and development efficiency across HBM programs. Partner with SoC Architecture, Verification, Physical Design, Firmware, and System teams to ensure successful end-to-end product execution. Work closely with Product Engineering, Test, Probe, Process Integration, Assembly, and Manufacturing to ensure robust, manufacturable HBM

Become a part of our caring community *(Selected candidate will be required to live within 60 mins of one of the following metro locations OR be willing to relocate to within 12 months of hire date: Louisville KY, NYC Metro, Dallas Metro, Charlotte NC Metro, Tampa, Miami, Washington DC metro, Chicago, Boston, Atlanta, Nashville) The Senior Security Architect for AI works with EIP Department leaders and Humana enterprise stakeholders to identify, define, and develop security architecture requirements and secure designs for AI technology solutions across Humana's business, information technology, and security domains. The Security Architect leads the development of technical architecture &amp; designs, develop security requirements, perform threat modeling and ensures alignment of security &amp; risk imperatives with business priorities. The Security Architect is responsible for the high-level design and patterns of security program infrastructures to enable the protection of Humana tools, data, systems, and networks. Working with EIP Leaders, the security architect drives alignment between the EIP security strategy, security architecture and infrastructure, and Humana's overall business and technology strategic priorities. In this capacity, the role is responsible for planning, designing, and proposing architectural patterns or security enhancements for Humana's information security and technology infrastructures. The role works with EIP and Humana leaders to review and reconcile Humana business priorities with EIP security requirements. The role engages with relevant EIP stakeholders to identify current and emerging security threats and works to design security architecture elements to mitigate threats as they emerge. Additionally, the role actively works to identify gaps within existing EIP reference architecture and designs updates to impacted sec

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Principal ASIC Design Engineer About the Role At Micron, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing. Micron’s Interface Pathfinding team drives performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. A core part of that work is silicon-based validation of novel PHY solutions, and we are growing the team to execute. As the Principal ASIC Design Engineer , you will be the primary digital contributor on a deliberately small, senior team — united around the goal of carrying high-speed interface technologies from architecture to tape-out. The team’s analog and chip-level architecture is anchored by a deeply experienced analog custom design engineer; your role is to be the authoritative digital voice — owning RTL design and micro-architecture of the digital blocks, defining timing constraints, supporting verification, and serving as the key interface between the digital design and the analog and layout specialists who will carry the implementation through to silicon. On a test ASIC of this scope, the front-end digital work is the critical path, with contractor and layout support engaged as bandwidth demands warrant. What You’ll Own Digital Block Architecture & RTL Design Own the micro-architecture and RTL implement

Leidos has an exciting opportunity for a Java Developer (SME) in our Intel Security Sector's Analysis Solutions Business Area . Our talented team is at the forefront in Security Engineering, Computer Network Operations (CNO), Mission Software, Analytical Methods and Modeling, Signals Intelligence (SIGINT), and Cryptographic Key Management. At Leidos , we offer competitive benefits , including Paid Time Off, 11 paid Holidays, 401K with a 6% company match and immediate vesting, Flexible Schedules, Discounted Stock Purchase Plans, Technical Upskilling, Education and Training Support, Parental Paid Leave, and much more. Join us and make a difference in National Security! Job Summary As a Java Developer you will to provide Agile DevOps support to mission critical systems. The candidate will provide technical expertise and support in the design, development, implementation and testing of the customer tools and applications in support of Extracting, Transforming and Loading data into an enterprise Data Lake. Based in a DevOps framework, the candidate will participate in and/or direct major deliverables of projects through all aspects of the software development lifecycle including scope and work estimation, architecture and design, coding and unit testing. This role requires the development of custom code/scripts to quickly extract, triage and exploit data across domains and data stores. Primary Responsibilities: Design, develop, test and maintain high-performance, scalable backend microservices using Java and the Spring Framework to meet customer information technology needs. Participates in and direct software programming initiatives, shaping backend architecture, mentoring team members, and conducting code reviews. Develops and directs software system validation and testing methods using Junit and Katalon and uses integrated custom develo

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Central Engineering at Micron Technology, Inc. is a dynamic and integral part of the company, focused on providing essential services and driving innovation across various technical domains. Established nearly five years ago, Central Engineering initially concentrated on creating economies of scale and enhancing efficiency for the Technology Products Group (TPG). Over the past three years, the team has evolved to deliver industry-first products, develop core design process automation, and produce powerful AI and Data Science tools. As a CAD in CE Memory CAD Engineer at Micron, we work in a fast-paced and collaborative environment. We provide production support role by evaluating, developing, enhancing and debugging both in-house and commercial EDA tools and flows for the design, physical layout, and verification of CMOS integrated circuits! The right person will have be developing and applying CAD software engineering methods, theories and research techniques in support of the organization's product development! Assignments include crafting and developing CAD software, assessing architecture and hardware limitations, and defining and implementing CAD software engineering applications. Responsibilities: Innovating to develop tools, flows, and methodologies to increase the design efficiency and quality of our memory designs on NAND/DRAM/HBM Providing training, documentation, and support to end-users o

Lead Analyst Company: The Boeing Company Boeing F-22 Mission Systems team is hiring for a Lead Analyst located in Berkeley, MO . As Lead Analyst, you will be responsible for analyzing engineering solutions for the F-22 Raptor, including both enhancing existing field units with the addition of new capabilities as well as architecting and testing completely new systems. In this role you will be joining a cross-functional team to progress our products through the development lifecycle. Position Responsibilities: Leads analysis and translation of complex requirements into system architecture, hardware and software designs and interface specifications. Must be able to work in a fast-paced, collaborative environment, engaging with multiple teams and being responsive to agile requirements and critical path customer need dates. Collaborates with Responsible Engineers, customer technical staff, suppliers, and Lockheed Martin teammates to develop and document complex electronic and electrical system requirements for F-22 avionics sub-systems and weapon system architecture Analyzes and translates requirements into system architecture, hardware and software designs and interface specifications in support of lab and operational environments Reviews test data, including off-nominal data, for accuracy, quality and/or fidelity prior to delivery to customer This position is expected to be 100% onsite. The selected candidate will be required to work onsite at one of the listed location options. This position requires the ability to obtain a US Secret Security Clearance for which the US Government requires US Citizenship A final Secret Clearance