System Power Engineer in United States

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role On the Accelerators team, you will help OpenAI evaluate and bring up new compute platforms that can support large-scale AI training and inference. Your work will range from prototyping system software on new accelerators to enabling performance optimizations across our AI workloads. You’ll work across the stack, collaborating with both hardware and software aspects - working on kernels, sharding strategies, scaling across distributed systems, and performance modeling. You'll help adapt OpenAI's software stack to non-traditional hardware and drive efficiency improvements in core AI workloads. This is not a compiler-focused role, rather bridging ML algorithms with system performance - especially at scale. In this role, you will: Prototype and enable OpenAI's AI software stack on new, exploratory accelerator platforms. Optimize large-scale model performance (LLMs, recommender systems, distributed AI workloads) for diverse hardware environments. Develop kernels, sharding mechanisms, and system scaling strategies tailored to emerging accelerators. Collaborate on optimizations at the model code level (e.g. PyTorch) and below to enhance performance on non-traditional hardware. Perform system-level performance modeling, debug bottlenecks, and drive end-to-end optimization. Work with hardware teams and vendors to evaluate alternatives to existing platforms and adapt the software stack to their architectures. Contribute to runtime improvements, compute/communication over

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role As a software engineer on the Scaling team, you’ll help build and optimize the low-level stack that orchestrates computation and data movement across OpenAI’s supercomputing clusters. Your work will involve designing high-performance runtimes, building custom kernels, contributing to compiler infrastructure, and developing scalable simulation systems to validate and optimize distributed training workloads. You will work at the intersection of systems programming, ML infrastructure, and high-performance computing, helping to create both ergonomic developer APIs and highly efficient runtime systems. This means balancing ease of use and introspection with the need for stability and performance on our evolving hardware fleet. This role is based in San Francisco, CA, with a hybrid work model (3 days/week in-office). Relocation assistance is available. In this role, you will: Design and build APIs and runtime components to orchestrate computation and data movement across heterogeneous ML workloads. Contribute to compiler infrastructure, including the development of optimizations and compiler passes to support evolving hardware. Engineer and optimize compute and data kernels, ensuring correctness, high performance, and portability across simulation and production environments. Profile and optimize system bottlenecks, especially around I/O, memory hierarchy, and interconnects, at both local and distributed scales. Develop simulation infrastructure to validate runtime b

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a systems-minded engineer to help advance our kernel development, performance engineering, and hardware-software co-design capabilities, with a particular focus on AI-assisted workflows and tooling. This person will work at the intersection of kernel optimization, developer tooling, observability, and research infrastructure, helping us improve both how production kernels are built and optimized, and how future hardware-software systems are designed and evaluated. The role is ideal for someone who is excited by low-level performance work, but also sees AI and automation as powerful tools for accelerating engineering velocity. You will help define the future of kernel engineering in the era of AI-assisted development. In this role, you may: Build developer tooling and workflows that make kernel development and performance optimization faster, more scalable, and easier to debug, integrate, and deploy. Develop observability, diagnostics, and validation infrastructure that makes AI-assisted optimization systems more interpretable, reliable, and effective. Optimize production kernels end to end by formulating optimization problems, running search loops, analyzing bottlenecks, debugging generated implementations, and landing improvements into production. Design abstractions, interfaces, and automation systems that accelerate kernel optimization, correctness validation, and hardware-software co-design. Improve AI-assisted optimization systems for sp

NVIDIA DGX Cloud is an AI Factory designed to power the next generation of AI and industrial-scale breakthroughs. As a Principal Engineer for Security Architecture, within our Security Engineering organization, you will own a core security domain of the AI factory: the architecture, the paved road that delivers it, and much of the code underneath. You will hold the security design bar across DGX Cloud from inside the teams doing the building, and this is a founding seat on a new team. Security Engineering is a new organization at DGX Cloud, accountable for the security outcome of the platform, and Security Architecture is the function inside it that holds the design bar. Security here is fleet horizontal and stack vertical, so your work will cross every DGX Cloud engineering organization: you will embed with the teams building GPU clusters, control planes, and services, join their designs as a participant rather than an approver, and leave behind systems in which an entire class of risk is no longer possible. There is no architecture review board here and no approval queue. You are a senior IC with deep security domain knowledge, and the security bar holds because you helped set it and then helped ship it. What You Will Be Doing: Own a Security Domain End to End: Take architectural ownership of a core domain of DGX Cloud security, from the design through the system running in production. That could be tenant and GPU workload isolation, workload identity, infrastructure and network, supply-chain provenance, hardened baselines and patching, or deploy-time policy and admission control. Embed with the Teams Building It: Join the design early, write the code, and help land it. The posture is not "you did this wrong." It is "here are the considerations we need to meet, I will help, let's go to work." Build Paved Roads, Not

About the Team OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. About the Role We are looking for an experienced Mechanical Engineer with 7+ years of experience in design of IT hardware from chip/package to system levels. You’ll work alongside experts in thermal, mechanical, electrical, software, and systems engineering to support the design, analysis, and validation of mechanical and thermal systems that ensure the reliability, efficiency, and longevity of mission-critical hardware. This position requires strong analytical skills, hands-on testing experience, and the ability to work in a fast-paced, cross-disciplinary environment. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Lead mechanical design for AI supercomputer product in the data center application Collaborate with the cross functional team to design and optimize thermal solutions for data center hardware, including chips, power modules, and system-level cooling architectures Collaborate with cross-functional teams to integrate thermal management strategies into hardware design, from concept to mass production Design and validate mechanical systems, including chassis, enclosures, cooling systems, and high-power connections, ensuring alignment with performance and reliability standards. Perform 3D modeling, FEA, tolerance analysis, and prototyping, ensuring manufacturability and a

NVIDIA is seeking a Senior Firmware Engineer to join our CSP Engagements team, focusing on system software for Datacenter products such as GB200. This role combines deep technical expertise in embedded firmware development with customer-facing responsibilities to enable cloud service providers with next-generation computing platforms. You will work at the intersection of hardware and software, driving technical solutions from concept through deployment. What you will be doing: Design and develop firmware solutions for manageability and observability of data center servers. Actively participate in hardware bring-up activities, OOB firmware development, protocol stacks (Redfish, PLDM, MCTP, NSM) and hardware-software co-design for Cloud Service Provider deployments. Debug and troubleshoot NVIDIA GPU firmware issues, power management, performance, and thermal control problems for data center deployments, providing active support to CSPs. Partner directly with CSPs to deliver technical solutions, co-develop & co-debug features and optimizations, and provide support during new product introductions. Perform advanced system debugging, root cause analysis, and performance optimization for large-scale data center environments. Collaborate with AE, FAE, and Solution Architect teams to deliver integrated customer solutions and technical documentation. What we need to see: Deep expertise in data center server architectures, HPC systems, and hardware-software co-design. Deep expertise in embedded firmware, server management controllers, and hardware bring-up with proven track record of shipping production BMC solutions Strong knowledge of DMTF protocols (Redfish, IPMI, PLDM, MCTP, SPDM), telemetry frameworks, and out-of-band management architectures Expert-level skills in C/C&

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role OpenAI's Hardware organization builds supercompute platforms from silicon and boards to full rack-scale systems to power advanced AI workloads. This role owns end-to-end quality for high-speed interconnect hardware across the product lifecycle: early design influence, supplier/contract manufacturer readiness, qualification, ramp, and fleet quality in lab and data center environments. You will be the quality lead for advanced interconnect components and assemblies, including high-speed copper cables, cable cartridges, patch panels, backplane/cable-backplane solutions, high-speed connectors, and related electro-mechanical interfaces. You will partner closely with electrical, mechanical, SI/PI, systems, reliability, operations, and external vendors to prevent escapes and drive rapid, data-driven containment and corrective action. In this role you will: Own quality for advanced interconnect components and assemblies: high-speed connectors, high-speed copper cables, cable cartridges (e.g., cable cassette style assemblies), patch panels & optics, and backplane/cable-backplane interconnect solutions. Drive quality-by-design: participate in design reviews, DFM/DFx, tolerance stacks, material and plating selections, connector mating strategy, strain relief, and assembly methods to reduce variation and field failures. Define and track quality and reliability metrics (DPPM, yield, escapes, RMA/FRACAS trends, Cpk/Ppk where applicable) for interconnects across NPI and m

About the Team OpenAI’s Infrastructure organization builds and evaluates the systems that power advanced AI workloads. We work closely with hardware, modeling, and architecture teams to ensure that new platforms deliver real-world performance aligned with workload needs. Our team focuses on understanding workload behavior across evolving hardware platforms—bridging the gap between theoretical capability and observed system performance. About the Role We are seeking a Workload Porting & Performance Engineer to evaluate new hardware platforms by porting benchmarks and real-world workloads, analyzing performance, and identifying system bottlenecks. In this role, you will bring up workloads on new systems, characterize performance behavior, and adapt workloads to better utilize hardware capabilities. You will play a critical role in validating new platforms and ensuring that performance aligns with expectations across compute, memory, and networking subsystems. This role requires strong hands-on experience with performance analysis, workload optimization, and system-level debugging across hardware and software boundaries. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance. Key Responsibilities Port and enable benchmarks and real-world workloads on new hardware platforms. Evaluate system performance across compute, memory, storage, and networking subsystems. Identify and analyze performance bottlenecks and inefficiencies. Adapt and optimize workloads to better utilize hardware capabilities. Develop and run performance experiments and profiling workflows. Compare expected vs. observed performance and provide feedback to: hardware architecture teams performance modeling teams system and software engineers. Debug issues across the stack, including software, runtime, and hardware interactions. Provide actionable insights to guide platform readiness and deployment decisions. Qualifications E

About Graphcore Graphcore is a global leader in artificial intelligence computing systems. We design advanced semiconductors and data center hardware that deliver the specialized processing power needed to advance AI while improving the efficiency required for broad adoption. As part of SoftBank Group, Graphcore belongs to a family of companies developing some of the world’s most transformative technologies. Our new AI Engineering Campus in Austin will play a central role in building the future of AI computing. The Opportunity As a Graduate Performance Engineer, you will contribute to the design, integration, bring-up, and validation of complex server- and rack-level performance of elaborate, large-scale systems. You will work alongside experienced engineers, software developer, and cross-functional partners while building practical skills in component, system and scale up/out performance optimization and design. Start: September, 2027 Location: Austin, Texas, USA What You’ll Do Support the design, peer review, bring-up, and debug of complex server- and rack-level systems. Assist with modeling, design and evaluation of the complete software and hardware stack identifying performance bottlenecks, possible solutions and testing those outcomes. Collaborate with many different teams across both hardware and software development and testing. What You’ll Bring A bachelor’s or master’s degree in electrical engineering, computer engineering, or a related discipline, completed before the role’s start date. Equivalent relevant education or practical experience will also be considered. Foundational knowledge of software development, hardware architecture and general understanding of performance implications. Hands-on experience gained through coursework, laboratories, internships, research, student projects, or personal projects. Ability to analyze technical problems, document your work, communicate clearly, and collaborate effectively. Curiosity, sound engineering judgment, a

NVIDIA's GPUs and SOCs are the world leaders in power, performance and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in the world through their contributions! This position will collaborate with Technical Package Lead and different design teams in the design and development of sophisticated, detailed layout of IC substrates for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues. What you'll be doing: As part of a Layout team, you will collaborate to implement high speed/density ASIC packages. Perform substrate breakout patterns for ASIC packages. Optimize package pinout incorporating system level trade-offs of pins assignment. Help perform package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite. Propose layout design trade-offs to the Technical Package Lead for resolution and implementation. Conduct design feasibility studies to evaluate the Package design goals for size, cost, and system performance. Develop symbols and CAD library databases using Cadence APD design tools Develop methodologies to improve layout productivity What we need to see: Hold a B.S. Electrical Engineering or equivalent experience 5+ years experience in PCB Layout of graphics cards, motherboards, line cards or other related technology. Experience with HDI designs is a plus Proven experience in substrate layout of wire bond and flip chip packages, preferred Significant background with Cadence AP

Manufacturing Test Engineer – Server Hardware Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin, which will play a central role in Graphcore's work building the future of AI computing. Role Overview We are seeking an experienced Manufacturing Test Engineer to support high-volume server manufacturing from board-level test through system-level production test. This role will work closely with an ODM manufacturing partner to define, implement, validate, and optimize the manufacturing test strategy for L6 board-level products , including ICT, MDA, and Board Functional Test , as well as support L10 system-level manufacturing test . The ideal candidate has strong experience in server hardware manufacturing, Linux-based test environments, diagnostic test coverage, fixture requirements, yield improvement, and root cause corrective action processes. This role requires both technical depth and hands-on manufacturing execution experience, with the ability to drive best practices across test development, factory readiness, quality planning, and ongoing production support. Key Responsibilities Manufacturing Test Strategy and Planning Work with ODM partners to define and execute the manufacturing test strategy for L6 board-level production . Develop and review test plans covering: In-Circuit Test, or ICT Manufacturing Defect Analyzer, or MDA Board Functional Test Diagnostic coverage requirements Manufacturing line test flow Fai

At Linear, we're building the product development system for teams and agents. AI is fundamentally changing how software gets built, and we’re shaping the tools this new era requires. Founded in 2019, Linear has become the platform of choice for more than 40,000 companies (including OpenAI, Coinbase, and Ramp) to plan, build, and ship their products. Today, our team is distributed across North America, Europe, and Australia, and we’re continuing to grow internationally. What unites us is relentless focus, fast execution, and a deep care for software craftsmanship. We’re looking for experienced engineers who have shipped applied AI systems to production and want to define what the agent-native future looks like. We are building intelligence into the core of Linear, enabling the product to orchestrate coding, proactively move work forward, and power-up every software team. You’ll work closely with product and design to transform foundation models into structured, reliable workflows embedded deeply in the core of Linear. We care deeply about keeping Linear fast, intuitive, and opinionated—AI is no exception. Location & work mode Linear is a remote-first company, with optional co-working offices in San Francisco, New York, and London. This role is open to candidates based in the North America. You can work from anywhere within this region. We value deep focus and async collaboration, with intentional moments to connect in person through team off-sites, optional co-working, and occasional travel. What you'll do Build AI-powered product features that feel native, fast, and delightful to use Work with product and design to prototype and iterate on intelligent workflows and user interactions Design backend services to power natural language interfaces, smart suggestions, agentic workloads, and more Optimize prompts, fine-tune model behavior, and evaluate performance Help to guide our agent platform, allowing third parties to bring agents into the core Linear experience

Shape the Future with Dun & Bradstreet At Dun & Bradstreet, we believe data has the power to create a better tomorrow. As a global leader in business decisioning data and analytics, we help companies worldwide grow, manage risk, and innovate. For over 180 years, businesses have trusted us to turn uncertainty into opportunity. We’re a diverse, global team that values creativity, collaboration, and bold ideas. Are you ready to make an impact and help shape what’s next? Join us! Explore opportunities at dnb.com/careers. Sr. Software Engineer – Duties are designing & developing service-oriented & resource-oriented software architecture using Python in Flask framework for e-commerce systems for scalable web-centric AWS & GCP application platforms & frameworks using SOAP & REST protocols & server-side GitHub REST API including performing requirements analysis; reviewing designs for new functionality; formulating detailed functional & product specifications; collaborating with cross-functional finance & product team leads; performing requirements functional decomposition, unit & integration testing; supporting technology upgrades through cloud migrations; performing SQL & NoSQL database tuning & maintenance; and providing technical documentation & system implementation support. Position requires Bachelor’s degree in Computer Science, Computer Engineering, Information Systems or a related field & 5 yrs exp in job duties as stated. Position is with Dun & Bradstreet located in Jacksonville, FL. Inquire and send resume through Dun & Bradstreet’s job board at https://jobs.lever.co/dnb. Position is under Senior Software Engineer for Jacksonville, FL. #LI-DNI

Job Details: Job Description: Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below. Life at Intel The Role and Impact As a System Software Architect, you will play a pivotal role in designing and developing innovative software solutions that drive efficiency and scalability across Intel's manufacturing processes. You will be responsible for architecting robust systems and frameworks that enhance operational performance while ensuring seamless integration with existing technologies. Your contributions will directly impact Intel's ability to deliver world-class semiconductor products efficiently and reliably. Business Group Intel Foundry Services is at the forefront of manufacturing excellence, delivering cutting-edge solutions to meet the complex demands of the semiconductor industry. The group focuses on pioneering advancements in manufacturing technologies, infrastructure optimization, and secure operations, enabling Intel to stay ahead in a fast-evolving landscape. By joining this team, you will contribute to Intel's broader mission of solving technological challenges and empowering innovation worldwide. Key Responsibilities: - Architect scalable and efficient system sof

About Graphcore Graphcore is a global leader in artificial intelligence computing systems. We design advanced semiconductors, software, and data center systems that provide the specialized processing power needed to advance AI while improving the efficiency required for broad adoption. As part of SoftBank Group, Graphcore belongs to a family of companies developing transformative technologies. Our U.S. engineering teams contribute to the hardware and software platforms that support the next generation of AI systems. The Opportunity We are looking for a recent graduate or early-career engineer to join the BMC Engineering team as a Graduate Firmware Engineer. You will develop low-level and embedded firmware that supports the operation, control, monitoring, and validation of advanced compute systems. You will work with experienced firmware, hardware, systems, and software engineers throughout the development lifecycle. The role combines hands-on implementation with automated testing, lab-based debugging, hardware bring-up, and analysis of interactions between firmware and the underlying platform. Start: September, 2027 Location: Austin, Texas, USA What You Will Do Design, implement, test, and maintain system and embedded firmware in C, C++, or Python. Take ownership of defined firmware features and deliver them from requirements and design through implementation, validation, and documentation. Develop and debug firmware in a Linux-based engineering environment using appropriate diagnostic tools and techniques. Create automated tests and scripts that improve firmware validation, test coverage, and engineering efficiency. Contribute to continuous integration and delivery workflows for firmware development and testing. Plan and conduct engineering experiments, analyze test data, and communicate findings clearly. Support lab setup, system configuration, hardware bring-up, and firmware validation on development platforms. Investigate firmware behavior and hardware-software