Yield Enhancement Engineer in United States

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron-Boise, ID, we are undergoing a historic $15 billion investment in semiconductor manufacturing; construction began in early 2023, with DRAM production slated for the second half of the decade. As a leader in the semiconductor industry, we build solutions that encourage and transform technology. With plans to invest more than $150 billion globally over the next decade in groundbreaking manufacturing, we are looking for hard-working people to join our Boise expansion team and give to the growth and innovation of the semiconductor industry. As a Senior Wet Etch Equipment Engineer , with a strong focus on safety and quality, you will play a meaningful role in improving our manufacturing processes by focusing on the installation, maintenance, optimization, and development of our wet etching equipment. Your expertise will give to the production of high-quality semiconductor components that are pivotal to our customers' success. You will work closely with multi-functional teams to tackle equipment issues and implement solutions that improve efficiency and yield. Your passion for engineering and willingness to learn will help us overcome the challenges of this fast-paced industry. We are looking for someone who enjoys hands-on work, values collaboration, and is eager to dive deep into the technical aspects of semiconductor manufacturing. This requisition is part of our talent pipeline for future opportunities. While we may not be actively hiring for this role today, we’re always looking to connect with gr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in artificial intelligence possible! We do it all while committing to integrity, sustainability, and giving back to our communities, because doing so can fuel the very innovation we are pursuing. As a process integration engineer in the DRAM organization, you will be part of a team of world-class engineers who are working in an industry leading 300mm R&D facility on technology which enables future memory scaling. You will focus on the performance and manufacturability of Micron’s cutting-edge next-generation memories. Areas of concentration will include integration and circuit issues specific to DRAM technology. In addition to a broad basis of process integration knowledge, this position will require a strong background in semiconductor device physics. Role interacts significantly with the process development, simulation, modeling, characterization, and reliability groups. Responsibilities include, but not limited to: Lead technology integration activities in enabling manufacturability of state-of-the-art DRAM technology Engage with numerous cross-functional teams including process development, product engineering, design, yield improvement, advanced mask and probe to arrive at solutions to

Job Details: Job Description: The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful. Join us as a Manufacturing Failure Analysis Engineer, where you'll play a pivotal role in ensuring the quality and reliability of Intel's next-generation silicon, product, package, platforms, and board process technologies. You will identify failures, conduct root cause analyses, and develop innovative methodologies to enhance performance and yield. By leveraging your expertise, you'll contribute to driving manufacturing innovation and supporting the delivery of world-class products. The ideal candidate brings hands-on experience in probing, strong understanding of device behavior, and the ability to independently execute complex debug workflows. Business group You will be part of Intel's manufacturing organization, a cornerstone of our operations that focuses on advancing semiconductor process technologies and ensuring product excellence. This team is dedicated to delivering high-quality solutions that support Intel's broader mission to create groundbreaking technologies that power the future. Key Responsibilities: • Operate general failure analysis tools in the labs, such as TEM, SEM, optical scopes. • Perform electrical probing an

Job Details: Job Description: As a Packaging Module Development Engineer, you will play a pivotal role in the development and optimization of Intel's assembly media and collaterals. Your daily work will involve designing innovative solutions to improve media and collateral reliability, manufacturability, and cost efficiency. Your contributions will directly support Intel's cutting-edge assembly packaging technology roadmap, driving advancements in semiconductor manufacturing processes. Business Group You will be part of Intel Corporation's Media Development organization, a team dedicated to advancing packaging technologies and manufacturing processes. This group operates at the forefront of innovation, enabling high-performance products and driving Intel's leadership in the semiconductor industry. By joining this collaborative environment, you will contribute to Intel's broader goals of delivering transformative technology solutions. Key Responsibilities Develop and optimize media and collaterals to meet quality, reliability, cost, yield, and productivity targets. Design and implement new media and collateral solutions, leveraging statistical methods like Design of Experiments (DOE) and Statistical Process Control (SPC). Conduct evaluations of media and collaterals under simulated field conditions, including tests for heat, humidity, temperature cycling, and dynamic forces. Lead initiatives to identify and mitigate media and collateral quality and reliability risks, utilizing innovative tools and methods. Provide technical consultation on media and collateral challenges and deliver solutions that align with operational and technology milestones. Document technical improvements and innovations through research papers and presentations. <p styl

Job Details: Job Description: The Intel Logic Technology development (LTD) organizations delivers process technology innovation to drive Intel's product roadmap. We give you opportunities to transform technology and create a better future by delivering products that touch the lives of every person on earth. As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results. We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and many more creative perks that make Intel a Great Place to Work. As a Process Integration Development Engineer, you will play a pivotal role in advancing Intel's semiconductor process technologies within the Logic Technology Development (LTD) group. Your day-to-day involves designing, optimizing, and implementing integrated process solutions that drive Intel's next-generation technology. By leveraging your expertise in process integration, yield analysis, and data-driven problem solving, you will contribute directly to the seamless transition of emerging technologies from development to high-volume manufacturing, ensuring Intel remains at the forefront of semiconductor innovation. Job Responsibilities include but are not limited to: ​ LTD Semiconductor Senior Process Integration Development Engineers are responsible for leading scientific research enabling the manufacture of innovative device architectures but not limited to: Lead scientific research enabling the manufacture of innovative device architectures coupled with the realization of these architectures. <li

Job Details: Job Description: Embark with us on a journey of growth and transformation as we create exceptionally engineered technology and bring AI everywhere. As a valued team member, your adaptability and attention to detail will contribute to our drive for results and relentless pursuit of quality, ensuring we meet our customers' needs with precision. Join us and build on our legacy of innovation and collaboration as we deliver world‑changing technology that improves the life of every person on the planet. Life at Intel: https://jobs.intel.com/en/life-at-intel This position is in the Intel Mask Operations within the Logic Technology Development team working in one of the most advanced semiconductor process technologies in the world. In this position the engineer will be an integral contributor to the ongoing production of photolithography masks for Intel's leading-edge silicon manufacturing solutions. In this position, you will work on-site, in a dynamic and collaborative environment solving complex and challenging technical problems on sophisticated manufacturing processes and equipment. As an IMO Module Development Engineer, the responsibilities may include but not limited to: Process equipment installation and development. Equipment maintenance, management of troubleshooting activities, regular monitoring of process performance, defect analysis and reduction. Drives improvements on quality, reliability, cost, yield, process stability/capability, productivity, and safety/ergonomics. Working with cross functional teams to solve technical process and defect issues. Plans and conducts experiments to fully characterize the process throughout the development cycle. Establishes control systems to optimize and sustain production performance. D

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Intro: The Advanced Packaging Technology Development (APTD) department at Micron Technology is advancing next-generation packaging technologies that enable the performance and scalability requirements of tomorrow’s AI and high-performance computing applications. Our team brings together experts in process integration, materials engineering, and semiconductor development to solve complex technical challenges and turn new ideas into production-ready solutions. Join us and help shape the future of advanced memory and packaging technology! Position Overview: As a Process Integration Engineer for Advanced Packaging, you will play a key role in developing and integrating advanced package architectures, including 2.5D, 3D stacking, HBM, and hybrid bonding technologies. You will work across engineering disciplines to develop new processes, improve performance and yield, and support the transfer of emerging technologies into manufacturing. This is an opportunity to contribute to innovative products while working on some of the industry's most advanced packaging solutions. Responsibilities: Develop and optimize advanced packaging technologies, including 2.5D/3D integration, HBM, hybrid bonding, and advanced interconnects Design and execute experiments to qualify materials, process flows, and design rules for new package architectures Analyze yield, performance, and defect data to identify process improvements using SPC and advanced analytics Drive

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our Vision Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever. Micron is advancing a historic $15 billion investment in semiconductor manufacturing in Boise, Idaho, with DRAM production planned for the second half of the decade. As a global leader in memory and storage solutions, Micron is investing more than $150 billion worldwide over the next decade to expand leading-edge manufacturing capabilities and drive innovation across the semiconductor industry. Join the Boise expansion team and help build the future of semiconductor manufacturing. You will work alongside experienced engineers to develop advanced processes, solve complex manufacturing challenges, and support the production of technologies that power everything from artificial intelligence to next-generation computing systems. Position Overview As a PCVD Process Engineer , you will contribute to the development, optimization, and sustainment of semiconductor manufacturing processes. You will gain hands-on experience in a state-of-the-art fabrication environment, partnering with teams to improve yield, quality, reliability, and productivity. This role offers an outstanding opportunity to apply engineering fundamentals, build technical expertise, and develop a career in advanced semi

The mission of The New York Times is to seek the truth and help people understand the world. That means independent journalism is at the heart of all we do as a company. It’s why we have a world-renowned newsroom that sends journalists to report on the ground from nearly 160 countries. It’s why we focus deeply on how our readers will experience our journalism, from print to audio to a world-class digital and app destination. And it’s why our business strategy centers on making journalism so good that it’s worth paying for. About the Role NYT Wirecutter is looking for a Senior Manager, Revenue Analytics to power our business strategy. Your core mandate is to increase audience monetization across our primary businesses—Affiliate, Advertising, and E-commerce—ensuring we preserve long-term audience trust. As a player-coach role, you will lead a team of analysts and partner closely with Revenue, Product, and Marketing leads to establish KPIs, run conversion experiments, and build attribution frameworks that scale revenue. You will report to the Executive Director, Data Analytics. Responsibilities You will lead, mentor, and onboard a team of two direct reports, nurturing their career growth You will analyze affiliate revenue drivers (e.g., merchant commissions, EPC, conversion rates, and partner yield) across all content touch points. You will be the analytics lead for the newly launched Wirecutter Store, reporting on unit economics, merchandise performance, cart funnel analytics, order value (AOV), and customer acquisition/repeat purchase metrics You will partner with Ad Ops and Advertising teams to track ad yield (RPM, eCPM), fill rates, and ad unit viewability, balancing display and custom content revenue against user experience and page speed You will evaluate trade-offs between affiliate links, ad placements, and Wirecutter Store product placements on site, creating a holistic monetization framework to maximize total revenue per user. You will lead recur

Job Details: Job Description: The Role and Impact As a Physical Design Engineer, you will play a critical role in driving the development of cutting-edge technologies at Intel. You will work hands-on to deliver high-performance physical designs, ensuring the successful integration of advanced semiconductor technologies. Your work will directly impact Intel's product innovation, addressing complex challenges in power, performance, and area optimization to shape the future of computing architectures. From synthesis to sign-off, your contributions will enable Intel to meet ambitious design goals and deliver transformative solutions to the market. Business Group This role is part of Intel's Corporate Technology Office (CTO), a dynamic group dedicated to advancing the company's technological leadership and innovation. The group focuses on developing foundational technologies, architectures, and methodologies that drive Intel's product roadmap and enable breakthrough computing solutions. Collaborating with cross-disciplinary teams, the CTO plays a pivotal role in delivering impactful designs that support Intel's broader mission of creating world-changing technology. Key Responsibilities - Drive RTL-to-GDS design convergence using advanced synthesis and place-and-route tools targeting performance, power, and area (PPA) goals. - Deliver block-level physical design, including closure of backend flows, electrical requirements, and enhancing silicon yield. - Collaborate with CAD and physical design methodology teams to adopt industry-leading tools and optimizations for custom designs. - Execute physical implementation tasks such as floor planning, bus/pin placement, power/clock distribution, congestion analysis, timing closure, IR drop analysis, and physical verification. - Debug timing, EM/IR, LVS, and DRC violations, and driv

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Vice President, Boise Front End Manufacturing Operations Location: Boise, Idaho Reports To: Senior Vice President, Global Front End Operations Position Summary Reporting to the Senior Vice President of Global Front End Operations, the Vice President, Boise Front End Manufacturing Operations is responsible for the overall leadership, performance, and strategic direction of Micron's Boise front-end manufacturing operations. This leader owns the safe, efficient, and predictable execution of all manufacturing activities while ensuring alignment with company objectives, technology roadmaps, customer requirements, and long-term capacity strategies. The Vice President serves as the senior operational leader for Boise manufacturing and is accountable for operational excellence across safety, quality, yield, cycle time, cost, delivery, workforce capability, and capacity utilization. As a member of the Global Front End Operations Leadership Team, the VP partners closely with Technology Development, Engineering, Business Units, Supply Chain, Procurement, Facilities, Quality, Finance, Human Resources, and peer manufacturing sites to drive world-class manufacturing performance and enterprise-wide outcomes. This leader will play a critical role in shaping the future of advanced semiconductor manufacturing through the deployment of next-generation technologies, automation, digital manufacturing capabilities, AI-enabled operations, and large-scale capacity expansions. Key Responsibilities<

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron has an opening for a Photolithography Engineer (Level 2 or 3) at our Boise, Idaho facility. This position is part of Micron’s Technology Development organization, where advanced ideas become manufacturable technologies. Our team works at the leading edge of memory innovation, partnering across design, integration, manufacturing, and equipment suppliers to enable the next generation of semiconductor devices. This is where curiosity, experimentation, and impact come together. As a Photolithography Engineer, you will play a key role in developing and integrating lithography processes that directly shape future memory technologies. You will work hands-on with tools, materials, layouts, and data, while leveraging Artificial Intelligence and other software, collaborating with global partners to move innovations from R&D into high-volume manufacturing. This role offers broad technical exposure and the opportunity to influence device performance, yield, and cost at scale. Responsibilities: Develop and integrate photolithography unit processes for advanced memory technologies Perform material evaluations, reticle, and layout development, OPC, overlay optimization, and process window analysis Drive yield improvement, failure analysis, and device performance optimization Partner with equipment vendors to evaluate tools and improve process capability Document processes, communicate results, and support technology transfer to manufacturing Leverage Artifi

NVIDIA’s Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first-principles thinking and engineering judgment at the highest level translate directly into product outcomes at scale. We are looking for a Principal Performance and Manufacturing Architect who has built the models, defined the specs, and seen them validated through silicon. You have owned the connection between design intent and manufacturing reality, not as a reviewer or a contributor, but as the person who set the methodology and proved it worked. You turn ambiguous physical phenomena into quantified, defensible margin terms. You do not wait for data to confirm your hypothesis; you design the experiment that gets it. You improve how the organization ships products after every program. The exceptional hire also uses AI deliberately — with proven workflow impact and the judgment to know where it compresses real work and where it introduces risk. What you'll be doing: Own the physics, from mechanism to margin. Build first-principles models connecting AVF, defect mechanisms, and DVFS transients to field FIT, system-level yield, and DPPM vs. coverage — calibrated per node and population shift — so every margin term in the V/F curve and P-state table is named, sourced, and defensible. Set the screen that resolves escapes. Specify ATE and SLT voltage, frequency, and timing conditions that capture worst-case transient VF windows — making it unambiguous whether a marginal defect or timing violation is detected or escapes at every manufacturing stage. Make the POR the authoritative source. Author the methodology document for each program and drive alignment across build, product definition, reliability, and test engineering — so every team is making decisions from the same model. Prove the model before produc

As one of the technology industry's most desirable employers, NVIDIA has been redefining accelerated computing, computer graphics and leading the Artificial Intelligence revolution. NVIDIA's innovation is fueled by its great technology—and amazing people. We are seeking a Senior Silicon and System Product Lead to influence, innovate and take our next generation products to the market. As part of the Silicon Solutions Team, we architect and deliver groundbreaking system solutions that integrate all aspects of the system from silicon design, software design to operations and final deployment in multiple market segments that NVIDIA serves. This position offers an unique opportunity to collaborate with multiple organizations in the company and grow your career in a high impact role. We need a passionate, hard-working and creative individual to lead the products all the way from market analysis to delivering the features on the final product. What you'll be doing: Drive product performance and power targets, trade-off features/configurations and provide innovative solutions to complex silicon and system level problems. Evaluate new market segments and use cases; translate market requirements to engineering problem statements and metrics. Innovate Performance, power, yield and quality optimizations and features for the world’s fastest power-shipping products in the GPU and SoC market segments spanning gaming, automotive, datacenter and DL/AI. Develop methodologies and requirements for multi-functional teams to drive silicon and system product features to production. Incorporate productization feedback to improve the next generation. Lead the team for feature requirements and schedule from architecture to silicon phase of projects. Work alongside system architects, designers, marketing teams, chip and board designers, software/firmware engineers, HW/S

NVIDIA's accelerated computing platforms move data at speeds that push the limits of what silicon and physics allow. Whether a high-speed interface trains reliably, maintains accurate margins, and survives every platform topology it will ever see is a question we answer ourselves. This role does that work. The Silicon Co-Design Group leads the boundary between what was designed and what was built. When a GPU, CPU, or SoC ships with interfaces that work at scale, this team is the reason. Most engineers debug within a layer. You will own the full stack. When an interface fails to train, the link margin is unexpectedly tight, or a customer reports a critical silicon issue, you trace the problem through protocol behavior, signal integrity, firmware, platform topology, and silicon marginalities. You then confirm that the fix works. Your methodology shapes how NVIDIA validates high-speed interfaces across generations. Your decisions affect yield, production ramp, and field quality. This is not a coordination role. The engineers who do it well hold protocol depth and system breadth simultaneously, never lose the thread across hardware, firmware, and software, and have the judgment to know when to go deeper and when to act. They are rare. Should that describe you, read on. What you'll be doing: Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness. Close the hardest failures. Drive root cause across protocol behavior, signal integrity, firmware and driver interactions, platform topology, and silicon marginalities and own every fix through to confirmation. Define validation strategy. Set test coverage, debug priorities, margining methodology, and stress criteria f