Architect- Memory Subsystem

NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems Engineer at NVIDIA, you'll join a group of hardworking engineers to develop and architect innovative Memory Solution for Tegra SoCs. In this position, you'll make a real impact in a multifaceted, technology-focused company. You will work with memory controller/PHY and Platform / System architect, Firmware, SI/PI, Memory suppliers to design and architect cutting edge, high speed and lower power memory technology for NVIDIA CPUs and SOCs. What You Will Be Doing: Analyze future DDR/LPDDR/HBM technologies to determine optimum performance, power, function and RAS in memory for Next generation SOC and Systems. Collaborate with ASIC Architects, Designers, Software and Firmware SW/FW teams to drive memory technology and associated requirements for memory controllers. Define Memory module, Package, and PCB layouts appropriate to the system workloads Debug and bring up memory evaluation / validation and failure issues on memory technology. Collaborate with DRAM suppliers and industry partners on to develop memory and memory related component technology. What We need to see: Bachelor's degree or master’s degree in Electrical Engineering, Computer Engineering (CE), or a related field (or equivalent experience) 10 years of proven track record in DRAM design, module design, or memory sub system design. Deep understanding and strong fundamental of memory design, features, ECC algorithm, SI and PI (Training algorithm) in DDR, LPDDR, and HBM. Strong understanding of memory sub system level interaction with Cache, Memory controller and PHY. Experience in the design, bring-up and validation for memory failure analysis Experience with Python, C/C

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: • Own and deliver critical HBM IO blocks and subsystems from architectural definition through circuit and RTL implementation, verification, tape-out, silicon bring-up, and post-silicon debug, including interfaces supporting future CPO systems. • Define HBM PHY, controller-to-PHY, die-to-die, clocking, training, calibration, power-management, error-handling, and test requirements for advanced heterogeneous systems. • Drive robust, high-performance builds by balancing bandwidth, latency, power, area, reliability, electrical signal quality, power stability, yield, and manufacturability trade-offs. • Lead architecture and design of analog, mixed-signal, and digital interface functions used in high-speed memory subsystems. • Partner with package, interposer, physical design, signal integrity, power integrity, and thermal teams to optimize interface implementation across 2.5D and 3D systems. • Lead root-cause analysis and resolution of complex pre-silicon and post-silicon issues across circuit design, RTL, architecture, process, package, interposer, and system interactions. • Serve as technical project lead for one or more advanced interface programs, coordinating execution across architecture, design, layout, verification, validation, packaging, test, and product engineering teams. • Define and communicate technical priorities, interface specifications, execution plans, risks, dependencies, and schedule impacts. • Work with internal teams, customers, IP pr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a System Architect in Advanced System Architecture Group at Micron Semiconductor Products, Inc., you will work with the memory industry's leading architecture team on new concepts that will craft the future of electronic systems around AI, servers, and mobile systems. You should be able leverage Artificial Intelligence for driving the processes and build next gen solutions with AI Supported frameworks. Your Responsibilities Will Include, But Are Not Limited To Delivering architectures and innovative solutions to optimize power and performance of next-generation memory and storage subsystems. Working with design and system architecture teams to identify key system requirements, seek the current bottlenecks and propose novel solutions for a wide range of applications. These activities will entail: Performing system-level simulations of innovative architectures to compare with existing design paradigms, using both open and closed-loop system performance analysis. Developing models of new controllers, components, memory devices, interconnects, and processors. Capturing, benchmarking, analyzing applications and their corresponding memory and storage access patterns. The scope of this analysis will span from the low-level software stack (operating system, drivers, etc…) down to the hardware and firmware controllers. You should have very strong knowledge of computer architecture and deep understanding sophisticated blocks such as caches, interconnects,

About the job Shape the SoC architecture behind Graphcore's next generation of AI acceleration platforms. Graphcore is expanding its Silicon Architecture Team in Bristol to deliver complex AI compute platforms. As a SoC Architect, you will define how critical subsystems are specified, modelled and integrated. You will turn product requirements into architecture choices across interfaces, interconnect, memory and platform behaviour. Your work will guide implementation, validation and trade-offs across multiple chip programmes. You will work with processor, SoC and system architects, plus design, verification, hardware and software teams. Together, you will evaluate IP, resolve integration questions and support silicon bring-up where needed. This is a rare chance to influence real AI silicon while Graphcore scales its contribution to SoftBank Group's AI ecosystem. The team and culture The team owns SoC architecture, subsystem modelling and system-level trade-offs across future AI acceleration platforms. Work moves from requirements to specifications, models, reviews and guidance for implementation teams. People here are expected to take responsibility early and keep decisions moving. You will speak directly with adjacent teams to clarify constraints, challenge assumptions and close open questions. Decisions are made through technical evidence, clear specifications and direct cross-functional discussion. The team values people who think big, act fast and speak up when architecture needs sharper choices. What we're looking for • Experience specifying or architecting complex SoC devices or subsystems. • Strong understanding of computer architecture, SoC integration, RTL development and verification processes. • Ability to turn product requirements into clear technical specifications and practical design trade-offs. • Software development capability, ideally with Python, C++, Rust or architecture modelling experience. • Knowledge of PCIe, LPDDR, DDR, E

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an Hardware Emulation Architect on the HBM architecture team you will be responsible for architecting, enabling, and deploying hardware emulation capabilities for next generation HBM products. You will work with design, verification, firmware, and system teams to determine emulation needs and opportunities. You will drive the development of hardware emulation ecosystem including procurement of hardware emulation platforms, creation of emulation testbenches and transactors, and development of emulation friendly verification IP. You will be responsible for proactively developing emulation capabilities to meet the needs of current and future products. You will also lead the effort to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Responsibilities will include, but are not limited to: Develop and maintain hardware emulation environments for complex SoCs and subsystems. Compile, configure, and debug large-scale RTL designs on emulation platforms (e.g., Palladium, Veloce, Zebu). Support pre-silicon validation, firmware bring-up, and early software development using emulation. Debug functional, performance, and connectivity issues across RTL, firmware, and system layers. Work closely with design, verification, firmware, and architecture teams to enable rapid debug and issue resolution. Create emulation testbenches, transactors, and models for system-level use cases. Enable hybrid validation flows (simulation + emulation

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron Technology, we transform how the world uses information to enrich life for all. The Heterogeneous Integration Group (HIG) develops next-generation High Bandwidth Memory (HBM) solutions that enable advanced AI, high-performance computing, data center, and networking applications. Our team collaborates across architecture, RTL design, verification, physical design, firmware, and product engineering to deliver innovative memory-centric SoC solutions that meet demanding power, performance, area, quality, and schedule objectives. As an HBM SoC Design Engineer/Architect, you will contribute to the design, integration, and validation of advanced HBM logic die and memory-centric SoCs. Working alongside experienced engineers, you will apply knowledge gained through academic coursework, research, internships, and engineering projects to solve real-world semiconductor design challenges. This role offers opportunities to develop expertise in digital design, ASIC development, HBM architecture, and AI-enabled engineering methodologies that improve design productivity and quality. Responsibilities Design, implement, and integrate digital logic and subsystem RTL using Verilog or SystemVerilog for next-generation HBM SoC solutions. Collaborate with architects and multi-functional engineering teams to translate functional requirements into microarchitectures, interface definitions, and implementation plans. Support design-quality activities including simulation, synthesis, static timing analy